1 #------------------------------------------------------------------------------
3 # Use ARMv6 instruction to operate on a single stack
5 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
7 # This program and the accompanying materials
8 # are licensed and made available under the terms and conditions of the BSD License
9 # which accompanies this distribution. The full text of the license may be found at
10 # http://opensource.org/licenses/bsd-license.php
12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #------------------------------------------------------------------------------
17 #include <Library/PcdLib.h>
21 This is the stack constructed by the exception handler (low address to high address)
22 # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
25 R0 0x00 # stmfd SP!,{R0-R12}
38 SP 0x34 # reserved via adding 0x20 (32) to the SP
47 LR 0x54 # SVC Link register (we need to restore it)
49 LR 0x58 # pushed by srsfd
55 GCC_ASM_EXPORT(ExceptionHandlersStart)
56 GCC_ASM_EXPORT(ExceptionHandlersEnd)
57 GCC_ASM_EXPORT(CommonExceptionEntry)
58 GCC_ASM_EXPORT(AsmCommonExceptionEntry)
59 GCC_ASM_EXPORT(CommonCExceptionHandler)
62 #if !defined(__APPLE__)
63 .fpu neon @ makes vpush/vpop assemble
69 // This code gets copied to the ARM vector table
70 // ExceptionHandlersStart - ExceptionHandlersEnd gets copied
72 ASM_PFX(ExceptionHandlersStart):
77 ASM_PFX(UndefinedInstruction):
78 b ASM_PFX(UndefinedInstructionEntry)
80 ASM_PFX(SoftwareInterrupt):
81 b ASM_PFX(SoftwareInterruptEntry)
83 ASM_PFX(PrefetchAbort):
84 b ASM_PFX(PrefetchAbortEntry)
87 b ASM_PFX(DataAbortEntry)
89 ASM_PFX(ReservedException):
90 b ASM_PFX(ReservedExceptionEntry)
99 srsdb #0x13! @ Store return state on SVC stack
100 @ We are already in SVC mode
102 stmfd SP!,{LR} @ Store the link register for the current mode
103 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
104 stmfd SP!,{R0-R12} @ Store the register state
106 mov R0,#0 @ ExceptionType
107 ldr R1,ASM_PFX(CommonExceptionEntry)
110 ASM_PFX(UndefinedInstructionEntry):
111 sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
112 srsdb #0x13! @ Store return state on SVC stack
113 cps #0x13 @ Switch to SVC for common stack
114 stmfd SP!,{LR} @ Store the link register for the current mode
115 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
116 stmfd SP!,{R0-R12} @ Store the register state
118 mov R0,#1 @ ExceptionType
119 ldr R1,ASM_PFX(CommonExceptionEntry)
122 ASM_PFX(SoftwareInterruptEntry):
123 sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
124 srsdb #0x13! @ Store return state on SVC stack
125 @ We are already in SVC mode
126 stmfd SP!,{LR} @ Store the link register for the current mode
127 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
128 stmfd SP!,{R0-R12} @ Store the register state
130 mov R0,#2 @ ExceptionType
131 ldr R1,ASM_PFX(CommonExceptionEntry)
134 ASM_PFX(PrefetchAbortEntry):
136 srsdb #0x13! @ Store return state on SVC stack
137 cps #0x13 @ Switch to SVC for common stack
138 stmfd SP!,{LR} @ Store the link register for the current mode
139 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
140 stmfd SP!,{R0-R12} @ Store the register state
142 mov R0,#3 @ ExceptionType
143 ldr R1,ASM_PFX(CommonExceptionEntry)
146 ASM_PFX(DataAbortEntry):
148 srsdb #0x13! @ Store return state on SVC stack
149 cps #0x13 @ Switch to SVC for common stack
150 stmfd SP!,{LR} @ Store the link register for the current mode
151 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
152 stmfd SP!,{R0-R12} @ Store the register state
155 ldr R1,ASM_PFX(CommonExceptionEntry)
158 ASM_PFX(ReservedExceptionEntry):
159 srsdb #0x13! @ Store return state on SVC stack
160 cps #0x13 @ Switch to SVC for common stack
161 stmfd SP!,{LR} @ Store the link register for the current mode
162 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
163 stmfd SP!,{R0-R12} @ Store the register state
166 ldr R1,ASM_PFX(CommonExceptionEntry)
171 srsdb #0x13! @ Store return state on SVC stack
172 cps #0x13 @ Switch to SVC for common stack
173 stmfd SP!,{LR} @ Store the link register for the current mode
174 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
175 stmfd SP!,{R0-R12} @ Store the register state
177 mov R0,#6 @ ExceptionType
178 ldr R1,ASM_PFX(CommonExceptionEntry)
183 srsdb #0x13! @ Store return state on SVC stack
184 cps #0x13 @ Switch to SVC for common stack
185 stmfd SP!,{LR} @ Store the link register for the current mode
186 sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
187 stmfd SP!,{R0-R12} @ Store the register state
188 @ Since we have already switch to SVC R8_fiq - R12_fiq
189 @ never get used or saved
190 mov R0,#7 @ ExceptionType
191 ldr R1,ASM_PFX(CommonExceptionEntry)
195 // This gets patched by the C code that patches in the vector table
197 ASM_PFX(CommonExceptionEntry):
198 .word ASM_PFX(AsmCommonExceptionEntry)
200 ASM_PFX(ExceptionHandlersEnd):
203 // This code runs from CpuDxe driver loaded address. It is patched into
204 // CommonExceptionEntry.
206 ASM_PFX(AsmCommonExceptionEntry):
207 mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
208 str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
210 mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
211 str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
213 mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
214 str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
216 mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
217 str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
219 ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
220 str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
222 add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
223 and R3, R1, #0x1f @ Check CPSR to see if User or System Mode
224 cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))
226 stmeqed R2, {lr}^ @ save unbanked lr
228 stmneed R2, {lr} @ save SVC lr
231 ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
232 @ Check to see if we have to adjust for Thumb entry
233 sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {
234 cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
237 tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
238 addne R5, R5, #2 @ PC += 2@
239 str R5,[SP,#0x58] @ Update LR value pused by srsfd
243 str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
245 sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
246 str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
248 @ R0 is ExceptionType
249 mov R1,SP @ R1 is SystemContext
251 #if (FixedPcdGet32(PcdVFPEnabled))
252 vpush {d0-d15} @ save vstm registers in case they are used in optimizations
258 CommonCExceptionHandler (
259 IN EFI_EXCEPTION_TYPE ExceptionType, R0
260 IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
264 blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
266 #if (FixedPcdGet32(PcdVFPEnabled))
270 ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
271 mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
273 ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
274 mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
276 ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
277 str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
279 ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
280 str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
282 add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry
283 add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
284 and R1, R1, #0x1f @ Check to see if User or System Mode
285 cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
287 ldmeqed R2, {lr}^ @ restore unbanked lr
289 ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}
291 ldmfd SP!,{R0-R12} @ Restore general purpose registers
292 @ Exception handler can not change SP
294 add SP,SP,#0x20 @ Clear out the remaining stack space
295 ldmfd SP!,{LR} @ restore the link register for this context
296 rfefd SP! @ return from exception via srsfd stack slot