3 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/IoLib.h>
16 #include <Drivers/PL390Gic.h>
19 * This function configures the all interrupts to be Non-secure.
24 PL390GicSetupNonSecure (
25 IN INTN GicDistributorBase
,
26 IN INTN GicInterruptInterfaceBase
29 UINTN CachedPriorityMask
= MmioRead32(GicInterruptInterfaceBase
+ GIC_ICCPMR
);
31 //Set priority Mask so that no interrupts get through to CPU
32 MmioWrite32(GicInterruptInterfaceBase
+ GIC_ICCPMR
, 0);
34 //Check if there are any pending interrupts
35 while(0 != (MmioRead32(GicDistributorBase
+ GIC_ICDICPR
) & 0xF))
37 //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
38 UINTN InterruptId
= MmioRead32(GicInterruptInterfaceBase
+ GIC_ICCIAR
);
40 //Write to End of interrupt signal
41 MmioWrite32(GicInterruptInterfaceBase
+ GIC_ICCEIOR
, InterruptId
);
44 // Ensure all GIC interrupts are Non-Secure
45 MmioWrite32(GicDistributorBase
+ GIC_ICDISR
, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
46 MmioWrite32(GicDistributorBase
+ GIC_ICDISR
+ 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
47 MmioWrite32(GicDistributorBase
+ GIC_ICDISR
+ 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
49 // Ensure all interrupts can get through the priority mask
50 MmioWrite32(GicInterruptInterfaceBase
+ GIC_ICCPMR
, CachedPriorityMask
);
55 PL390GicEnableInterruptInterface (
56 IN INTN GicInterruptInterfaceBase
59 MmioWrite32(GicInterruptInterfaceBase
+ GIC_ICCPMR
, 0x000000FF); /* Set Priority Mask to allow interrupts */
62 * Enable CPU interface in Secure world
63 * Enable CPU inteface in Non-secure World
64 * Signal Secure Interrupts to CPU using FIQ line *
66 MmioWrite32(GicInterruptInterfaceBase
+ GIC_ICCICR
,
67 GIC_ICCICR_ENABLE_SECURE(1) |
68 GIC_ICCICR_ENABLE_NS(1) |
69 GIC_ICCICR_ACK_CTL(0) |
70 GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
71 GIC_ICCICR_USE_SBPR(0));
76 PL390GicEnableDistributor (
77 IN INTN GicDistributorBase
80 MmioWrite32(GicDistributorBase
+ GIC_ICDDCR
, 1); // turn on the GIC distributor
86 IN INTN GicDistributorBase
,
87 IN INTN TargetListFilter
,
91 MmioWrite32(GicDistributorBase
+ GIC_ICDSGIR
, ((TargetListFilter
& 0x3) << 24) | ((CPUTargetList
& 0xFF) << 16));
96 PL390GicAcknowledgeSgiFrom (
97 IN INTN GicInterruptInterfaceBase
,
103 InterruptId
= MmioRead32(GicInterruptInterfaceBase
+ GIC_ICCIAR
);
105 //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
106 if (((CoreId
& 0x7) << 10) == (InterruptId
& 0x1C00)) {
107 //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
108 MmioWrite32(GicInterruptInterfaceBase
+ GIC_ICCEIOR
, InterruptId
);
117 PL390GicAcknowledgeSgi2From (
118 IN INTN GicInterruptInterfaceBase
,
125 InterruptId
= MmioRead32(GicInterruptInterfaceBase
+ GIC_ICCIAR
);
127 //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
128 if((((CoreId
& 0x7) << 10) | (SgiId
& 0x3FF)) == (InterruptId
& 0x1FFF)) {
129 //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
130 MmioWrite32(GicInterruptInterfaceBase
+ GIC_ICCEIOR
, InterruptId
);