3 * Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
5 * SPDX-License-Identifier: BSD-2-Clause-Patent
12 #include <Library/ArmGicArchLib.h>
15 #define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
16 #define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
17 #define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
19 // Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
20 #define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
21 #define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
22 #define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
23 #define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
24 #define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
25 #define ARM_GIC_ICDABR 0x300 // Active Bit Registers
27 // Each reg base below repeats for Number of interrupts / 4
28 #define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
30 // Each reg base below repeats for Number of interrupts
31 #define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
32 #define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
34 #define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
37 #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
39 // GICv3 specific registers
40 #define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
43 #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
44 #define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
47 #define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register
48 #define ARM_GIC_ICDICFR_BYTES (ARM_GIC_ICDICFR_WIDTH / 8)
49 #define ARM_GIC_ICDICFR_F_WIDTH 2 // Each F field is 2 bits
50 #define ARM_GIC_ICDICFR_F_STRIDE 16 // (32/2) F fields per register
51 #define ARM_GIC_ICDICFR_F_CONFIG1_BIT 1 // Bit number within F field
52 #define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt
53 #define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt
56 #define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
57 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
58 #define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
59 #define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
61 // GIC Redistributor Control frame
62 #define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
64 // GIC Redistributor TYPER bit assignments
65 #define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
66 #define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
67 #define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
68 #define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
69 #define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
71 #define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
72 #define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
73 #define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
75 #define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \
76 ARM_GICR_TYPER_AFFINITY) >> 32)
78 // GIC SGI & PPI Redistributor frame
79 #define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
80 #define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
83 #define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
84 #define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
85 #define ARM_GIC_ICCBPR 0x08 // Binary Point Register
86 #define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
87 #define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
88 #define ARM_GIC_ICCRPR 0x14 // Running Priority Register
89 #define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
90 #define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
91 #define ARM_GIC_ICCIIDR 0xFC // Identification Register
93 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
94 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
95 #define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
97 // Bit-masks to configure the CPU Interface Control register
98 #define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
99 #define ARM_GIC_ICCICR_ENABLE_NS 0x02
100 #define ARM_GIC_ICCICR_ACK_CTL 0x04
101 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
102 #define ARM_GIC_ICCICR_USE_SBPR 0x10
104 // Bit Mask for GICC_IIDR
105 #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
106 #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
107 #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
108 #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
111 #define ARM_GIC_ICCIAR_ACKINTID 0x3FF
115 ArmGicGetInterfaceIdentification (
116 IN INTN GicInterruptInterfaceBase
119 // GIC Secure interfaces
122 ArmGicSetupNonSecure (
124 IN INTN GicDistributorBase
,
125 IN INTN GicInterruptInterfaceBase
130 ArmGicSetSecureInterrupts (
131 IN UINTN GicDistributorBase
,
132 IN UINTN
*GicSecureInterruptMask
,
133 IN UINTN GicSecureInterruptMaskSize
138 ArmGicEnableInterruptInterface (
139 IN INTN GicInterruptInterfaceBase
144 ArmGicDisableInterruptInterface (
145 IN INTN GicInterruptInterfaceBase
150 ArmGicEnableDistributor (
151 IN INTN GicDistributorBase
156 ArmGicDisableDistributor (
157 IN INTN GicDistributorBase
162 ArmGicGetMaxNumInterrupts (
163 IN INTN GicDistributorBase
169 IN INTN GicDistributorBase
,
170 IN INTN TargetListFilter
,
171 IN INTN CPUTargetList
,
176 * Acknowledge and return the value of the Interrupt Acknowledge Register
178 * InterruptId is returned separately from the register value because in
179 * the GICv2 the register value contains the CpuId and InterruptId while
180 * in the GICv3 the register value is only the InterruptId.
182 * @param GicInterruptInterfaceBase Base Address of the GIC CPU Interface
183 * @param InterruptId InterruptId read from the Interrupt
184 * Acknowledge Register
186 * @retval value returned by the Interrupt Acknowledge Register
191 ArmGicAcknowledgeInterrupt (
192 IN UINTN GicInterruptInterfaceBase
,
193 OUT UINTN
*InterruptId
198 ArmGicEndOfInterrupt (
199 IN UINTN GicInterruptInterfaceBase
,
205 ArmGicSetPriorityMask (
206 IN INTN GicInterruptInterfaceBase
,
212 ArmGicSetInterruptPriority (
213 IN UINTN GicDistributorBase
,
214 IN UINTN GicRedistributorBase
,
221 ArmGicEnableInterrupt (
222 IN UINTN GicDistributorBase
,
223 IN UINTN GicRedistributorBase
,
229 ArmGicDisableInterrupt (
230 IN UINTN GicDistributorBase
,
231 IN UINTN GicRedistributorBase
,
237 ArmGicIsInterruptEnabled (
238 IN UINTN GicDistributorBase
,
239 IN UINTN GicRedistributorBase
,
243 // GIC revision 2 specific declarations
245 // Interrupts from 1020 to 1023 are considered as special interrupts
246 // (eg: spurious interrupts)
247 #define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \
248 (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
252 ArmGicV2SetupNonSecure (
254 IN INTN GicDistributorBase
,
255 IN INTN GicInterruptInterfaceBase
260 ArmGicV2EnableInterruptInterface (
261 IN INTN GicInterruptInterfaceBase
266 ArmGicV2DisableInterruptInterface (
267 IN INTN GicInterruptInterfaceBase
272 ArmGicV2AcknowledgeInterrupt (
273 IN UINTN GicInterruptInterfaceBase
278 ArmGicV2EndOfInterrupt (
279 IN UINTN GicInterruptInterfaceBase
,
283 // GIC revision 3 specific declarations
285 #define ICC_SRE_EL2_SRE (1 << 0)
287 #define ARM_GICD_IROUTER_IRM BIT31
291 ArmGicV3GetControlSystemRegisterEnable (
297 ArmGicV3SetControlSystemRegisterEnable (
298 IN UINT32 ControlSystemRegisterEnable
303 ArmGicV3EnableInterruptInterface (
309 ArmGicV3DisableInterruptInterface (
315 ArmGicV3AcknowledgeInterrupt (
321 ArmGicV3EndOfInterrupt (
326 ArmGicV3SetBinaryPointer (
331 ArmGicV3SetPriorityMask (