ArmPkg/Include/Library/ArmGicLib.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2018, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef __ARMGIC_H
  16 #define __ARMGIC_H
  17
  18 #include <Library/ArmGicArchLib.h>
  19
  20 // GIC Distributor
  21 #define ARM_GIC_ICDDCR          0x000 // Distributor Control Register
  22 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register
  23 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register
  24
  25 // Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
  26 #define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers
  27 #define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers
  28 #define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers
  29 #define ARM_GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers
  30 #define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers
  31 #define ARM_GIC_ICDABR          0x300 // Active Bit Registers
  32
  33 // Each reg base below repeats for Number of interrupts / 4
  34 #define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers
  35
  36 // Each reg base below repeats for Number of interrupts
  37 #define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers
  38 #define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers
  39
  40 #define ARM_GIC_ICDPPISR        0xD00 // PPI Status register
  41
  42 // just one of these
  43 #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register
  44
  45 // GICv3 specific registers
  46 #define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers
  47
  48 // GICD_CTLR bits
  49 #define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)
  50 #define ARM_GIC_ICDDCR_DS       (1 << 6) // Disable Security (DS)
  51
  52 // GICD_ICDICFR bits
  53 #define ARM_GIC_ICDICFR_WIDTH            32   // ICDICFR is a 32 bit register
  54 #define ARM_GIC_ICDICFR_BYTES            (ARM_GIC_ICDICFR_WIDTH / 8)
  55 #define ARM_GIC_ICDICFR_F_WIDTH          2    // Each F field is 2 bits
  56 #define ARM_GIC_ICDICFR_F_STRIDE         16   // (32/2) F fields per register
  57 #define ARM_GIC_ICDICFR_F_CONFIG1_BIT    1    // Bit number within F field
  58 #define ARM_GIC_ICDICFR_LEVEL_TRIGGERED  0x0  // Level triggered interrupt
  59 #define ARM_GIC_ICDICFR_EDGE_TRIGGERED   0x1  // Edge triggered interrupt
  60
  61
  62 // GIC Redistributor
  63 #define ARM_GICR_CTLR_FRAME_SIZE         SIZE_64KB
  64 #define ARM_GICR_SGI_PPI_FRAME_SIZE      SIZE_64KB
  65 #define ARM_GICR_SGI_VLPI_FRAME_SIZE     SIZE_64KB
  66 #define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
  67
  68 // GIC Redistributor Control frame
  69 #define ARM_GICR_TYPER          0x0008  // Redistributor Type Register
  70
  71 // GIC Redistributor TYPER bit assignments
  72 #define ARM_GICR_TYPER_PLPIS        (1 << 0)              // Physical LPIs
  73 #define ARM_GICR_TYPER_VLPIS        (1 << 1)              // Virtual LPIs
  74 #define ARM_GICR_TYPER_DIRECTLPI    (1 << 3)              // Direct LPIs
  75 #define ARM_GICR_TYPER_LAST         (1 << 4)              // Last Redistributor in series
  76 #define ARM_GICR_TYPER_DPGS         (1 << 5)              // Disable Processor Group
  77                                                           // Selection Support
  78 #define ARM_GICR_TYPER_PROCNO       (0xFFFF << 8)         // Processor Number
  79 #define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24)           // Common LPI Affinity
  80 #define ARM_GICR_TYPER_AFFINITY     (0xFFFFFFFFULL << 32) // Redistributor Affinity
  81
  82 #define ARM_GICR_TYPER_GET_AFFINITY(TypeReg)  (((TypeReg) & \
  83                                                 ARM_GICR_TYPER_AFFINITY) >> 32)
  84
  85 // GIC SGI & PPI Redistributor frame
  86 #define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers
  87 #define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers
  88
  89 // GIC Cpu interface
  90 #define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register
  91 #define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register
  92 #define ARM_GIC_ICCBPR          0x08  // Binary Point Register
  93 #define ARM_GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register
  94 #define ARM_GIC_ICCEIOR         0x10  // End Of Interrupt Register
  95 #define ARM_GIC_ICCRPR          0x14  // Running Priority Register
  96 #define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register
  97 #define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register
  98 #define ARM_GIC_ICCIIDR         0xFC  // Identification Register
  99
 100 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0
 101 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1
 102 #define ARM_GIC_ICDSGIR_FILTER_ITSELF           0x2
 103
 104 // Bit-masks to configure the CPU Interface Control register
 105 #define ARM_GIC_ICCICR_ENABLE_SECURE            0x01
 106 #define ARM_GIC_ICCICR_ENABLE_NS                0x02
 107 #define ARM_GIC_ICCICR_ACK_CTL                  0x04
 108 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ     0x08
 109 #define ARM_GIC_ICCICR_USE_SBPR                 0x10
 110
 111 // Bit Mask for GICC_IIDR
 112 #define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr)   (((IccIidr) >> 20) & 0xFFF)
 113 #define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
 114 #define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr)     (((IccIidr) >> 12) & 0xF)
 115 #define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr)  ((IccIidr) & 0xFFF)
 116
 117 // Bit Mask for
 118 #define ARM_GIC_ICCIAR_ACKINTID                 0x3FF
 119
 120 UINTN
 121 EFIAPI
 122 ArmGicGetInterfaceIdentification (
 123   IN  INTN          GicInterruptInterfaceBase
 124   );
 125
 126 // GIC Secure interfaces
 127 VOID
 128 EFIAPI
 129 ArmGicSetupNonSecure (
 130   IN  UINTN         MpId,
 131   IN  INTN          GicDistributorBase,
 132   IN  INTN          GicInterruptInterfaceBase
 133   );
 134
 135 VOID
 136 EFIAPI
 137 ArmGicSetSecureInterrupts (
 138   IN  UINTN         GicDistributorBase,
 139   IN  UINTN*        GicSecureInterruptMask,
 140   IN  UINTN         GicSecureInterruptMaskSize
 141   );
 142
 143 VOID
 144 EFIAPI
 145 ArmGicEnableInterruptInterface (
 146   IN  INTN          GicInterruptInterfaceBase
 147   );
 148
 149 VOID
 150 EFIAPI
 151 ArmGicDisableInterruptInterface (
 152   IN  INTN          GicInterruptInterfaceBase
 153   );
 154
 155 VOID
 156 EFIAPI
 157 ArmGicEnableDistributor (
 158   IN  INTN          GicDistributorBase
 159   );
 160
 161 VOID
 162 EFIAPI
 163 ArmGicDisableDistributor (
 164   IN  INTN          GicDistributorBase
 165   );
 166
 167 UINTN
 168 EFIAPI
 169 ArmGicGetMaxNumInterrupts (
 170   IN  INTN          GicDistributorBase
 171   );
 172
 173 VOID
 174 EFIAPI
 175 ArmGicSendSgiTo (
 176   IN  INTN          GicDistributorBase,
 177   IN  INTN          TargetListFilter,
 178   IN  INTN          CPUTargetList,
 179   IN  INTN          SgiId
 180   );
 181
 182 /*
 183  * Acknowledge and return the value of the Interrupt Acknowledge Register
 184  *
 185  * InterruptId is returned separately from the register value because in
 186  * the GICv2 the register value contains the CpuId and InterruptId while
 187  * in the GICv3 the register value is only the InterruptId.
 188  *
 189  * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface
 190  * @param InterruptId                 InterruptId read from the Interrupt
 191  *                                    Acknowledge Register
 192  *
 193  * @retval value returned by the Interrupt Acknowledge Register
 194  *
 195  */
 196 UINTN
 197 EFIAPI
 198 ArmGicAcknowledgeInterrupt (
 199   IN  UINTN          GicInterruptInterfaceBase,
 200   OUT UINTN          *InterruptId
 201   );
 202
 203 VOID
 204 EFIAPI
 205 ArmGicEndOfInterrupt (
 206   IN  UINTN                 GicInterruptInterfaceBase,
 207   IN UINTN                  Source
 208   );
 209
 210 UINTN
 211 EFIAPI
 212 ArmGicSetPriorityMask (
 213   IN  INTN          GicInterruptInterfaceBase,
 214   IN  INTN          PriorityMask
 215   );
 216
 217 VOID
 218 EFIAPI
 219 ArmGicEnableInterrupt (
 220   IN UINTN                  GicDistributorBase,
 221   IN UINTN                  GicRedistributorBase,
 222   IN UINTN                  Source
 223   );
 224
 225 VOID
 226 EFIAPI
 227 ArmGicDisableInterrupt (
 228   IN UINTN                  GicDistributorBase,
 229   IN UINTN                  GicRedistributorBase,
 230   IN UINTN                  Source
 231   );
 232
 233 BOOLEAN
 234 EFIAPI
 235 ArmGicIsInterruptEnabled (
 236   IN UINTN                  GicDistributorBase,
 237   IN UINTN                  GicRedistributorBase,
 238   IN UINTN                  Source
 239   );
 240
 241 // GIC revision 2 specific declarations
 242
 243 // Interrupts from 1020 to 1023 are considered as special interrupts
 244 // (eg: spurious interrupts)
 245 #define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \
 246           (((Interrupt) >= 1020) && ((Interrupt) <= 1023))
 247
 248 VOID
 249 EFIAPI
 250 ArmGicV2SetupNonSecure (
 251   IN  UINTN         MpId,
 252   IN  INTN          GicDistributorBase,
 253   IN  INTN          GicInterruptInterfaceBase
 254   );
 255
 256 VOID
 257 EFIAPI
 258 ArmGicV2EnableInterruptInterface (
 259   IN  INTN          GicInterruptInterfaceBase
 260   );
 261
 262 VOID
 263 EFIAPI
 264 ArmGicV2DisableInterruptInterface (
 265   IN  INTN          GicInterruptInterfaceBase
 266   );
 267
 268 UINTN
 269 EFIAPI
 270 ArmGicV2AcknowledgeInterrupt (
 271   IN  UINTN          GicInterruptInterfaceBase
 272   );
 273
 274 VOID
 275 EFIAPI
 276 ArmGicV2EndOfInterrupt (
 277   IN UINTN                  GicInterruptInterfaceBase,
 278   IN UINTN                  Source
 279   );
 280
 281 // GIC revision 3 specific declarations
 282
 283 #define ICC_SRE_EL2_SRE         (1 << 0)
 284
 285 #define ARM_GICD_IROUTER_IRM BIT31
 286
 287 UINT32
 288 EFIAPI
 289 ArmGicV3GetControlSystemRegisterEnable (
 290   VOID
 291   );
 292
 293 VOID
 294 EFIAPI
 295 ArmGicV3SetControlSystemRegisterEnable (
 296   IN UINT32         ControlSystemRegisterEnable
 297   );
 298
 299 VOID
 300 EFIAPI
 301 ArmGicV3EnableInterruptInterface (
 302   VOID
 303   );
 304
 305 VOID
 306 EFIAPI
 307 ArmGicV3DisableInterruptInterface (
 308   VOID
 309   );
 310
 311 UINTN
 312 EFIAPI
 313 ArmGicV3AcknowledgeInterrupt (
 314   VOID
 315   );
 316
 317 VOID
 318 EFIAPI
 319 ArmGicV3EndOfInterrupt (
 320   IN UINTN                  Source
 321   );
 322
 323 VOID
 324 ArmGicV3SetBinaryPointer (
 325   IN UINTN                  BinaryPoint
 326   );
 327
 328 VOID
 329 ArmGicV3SetPriorityMask (
 330   IN UINTN                  Priority
 331   );
 332
 333 #endif