3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
13 #include <Uefi/UefiBaseType.h>
16 #include <Chipset/ArmV7.h>
17 #elif defined(MDE_CPU_AARCH64)
18 #include <Chipset/AArch64.h>
20 #error "Unknown chipset."
23 #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
24 EFI_MEMORY_WT | EFI_MEMORY_WB | \
28 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
30 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
31 * be used in Secure World to distinguished Secure to Non-Secure memory.
34 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
35 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
,
36 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
37 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
,
39 // On some platforms, memory mapped flash region is designed as not supporting
40 // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
42 // Do NOT use below two attributes if you are not sure.
43 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE
,
44 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE
,
46 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
47 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
,
48 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
49 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
50 } ARM_MEMORY_REGION_ATTRIBUTES
;
52 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
55 EFI_PHYSICAL_ADDRESS PhysicalBase
;
56 EFI_VIRTUAL_ADDRESS VirtualBase
;
58 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
59 } ARM_MEMORY_REGION_DESCRIPTOR
;
61 typedef VOID (*CACHE_OPERATION
)(VOID
);
62 typedef VOID (*LINE_OPERATION
)(UINTN
);
68 ARM_PROCESSOR_MODE_USER
= 0x10,
69 ARM_PROCESSOR_MODE_FIQ
= 0x11,
70 ARM_PROCESSOR_MODE_IRQ
= 0x12,
71 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
72 ARM_PROCESSOR_MODE_ABORT
= 0x17,
73 ARM_PROCESSOR_MODE_HYP
= 0x1A,
74 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
75 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
76 ARM_PROCESSOR_MODE_MASK
= 0x1F
82 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
83 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
84 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
85 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
86 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
87 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
89 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
90 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
91 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
92 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
93 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
94 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
99 #define ARM_CORE_AFF0 0xFF
100 #define ARM_CORE_AFF1 (0xFF << 8)
101 #define ARM_CORE_AFF2 (0xFF << 16)
102 #define ARM_CORE_AFF3 (0xFFULL << 32)
104 #define ARM_CORE_MASK ARM_CORE_AFF0
105 #define ARM_CLUSTER_MASK ARM_CORE_AFF1
106 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
107 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
108 #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
109 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
113 ArmDataCacheLineLength (
119 ArmInstructionCacheLineLength (
125 ArmCacheWritebackGranule (
131 ArmIsArchTimerImplemented (
161 ArmInvalidateDataCache (
168 ArmCleanInvalidateDataCache (
180 ArmInvalidateInstructionCache (
186 ArmInvalidateDataCacheEntryByMVA (
192 ArmCleanDataCacheEntryToPoUByMVA (
198 ArmInvalidateInstructionCacheEntryToPoUByMVA (
204 ArmCleanDataCacheEntryByMVA (
210 ArmCleanInvalidateDataCacheEntryByMVA (
222 ArmDisableDataCache (
228 ArmEnableInstructionCache (
234 ArmDisableInstructionCache (
252 ArmEnableCachesAndMmu (
258 ArmDisableCachesAndMmu (
264 ArmEnableInterrupts (
270 ArmDisableInterrupts (
276 ArmGetInterruptState (
282 ArmEnableAsynchronousAbort (
288 ArmDisableAsynchronousAbort (
323 * Invalidate Data and Instruction TLBs
333 ArmUpdateTranslationTableEntry (
334 IN VOID
*TranslationTableEntry
,
340 ArmSetDomainAccessControl (
347 IN VOID
*TranslationTableBase
358 ArmGetTTBR0BaseAddress (
370 ArmEnableBranchPrediction (
376 ArmDisableBranchPrediction (
394 ArmDataMemoryBarrier (
400 ArmDataSynchronizationBarrier (
406 ArmInstructionSynchronizationBarrier (
496 Get the Secure Configuration Register value
498 @return Value read from the Secure Configuration Register
508 Set the Secure Configuration Register
510 @param Value Value to write to the Secure Configuration Register
528 IN UINT32 VectorMonitorBase
552 IN UINTN HypModeVectorBase
557 // Helper functions for accessing CPU ACTLR
580 ArmUnsetCpuActlrBit (
585 // Accessors for the architected generic timer registers
588 #define ARM_ARCH_TIMER_ENABLE (1 << 0)
589 #define ARM_ARCH_TIMER_IMASK (1 << 1)
590 #define ARM_ARCH_TIMER_ISTATUS (1 << 2)
714 ArmGetPhysicalAddressBits (
718 #endif // __ARM_LIB__