3 Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 ARM_CACHE_TYPE_WRITE_BACK
,
20 ARM_CACHE_TYPE_UNKNOWN
24 ARM_CACHE_ARCHITECTURE_UNIFIED
,
25 ARM_CACHE_ARCHITECTURE_SEPARATE
,
26 ARM_CACHE_ARCHITECTURE_UNKNOWN
27 } ARM_CACHE_ARCHITECTURE
;
31 ARM_CACHE_ARCHITECTURE Architecture
;
32 BOOLEAN DataCachePresent
;
34 UINTN DataCacheAssociativity
;
35 UINTN DataCacheLineLength
;
36 BOOLEAN InstructionCachePresent
;
37 UINTN InstructionCacheSize
;
38 UINTN InstructionCacheAssociativity
;
39 UINTN InstructionCacheLineLength
;
43 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
,
44 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
45 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
46 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
47 } ARM_MEMORY_REGION_ATTRIBUTES
;
53 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
54 } ARM_MEMORY_REGION_DESCRIPTOR
;
56 typedef VOID (*CACHE_OPERATION
)(VOID
);
57 typedef VOID (*LINE_OPERATION
)(UINTN
);
60 ARM_PROCESSOR_MODE_USER
= 0x10,
61 ARM_PROCESSOR_MODE_FIQ
= 0x11,
62 ARM_PROCESSOR_MODE_IRQ
= 0x12,
63 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
64 ARM_PROCESSOR_MODE_ABORT
= 0x17,
65 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
66 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
67 ARM_PROCESSOR_MODE_MASK
= 0x1F
76 ARM_CACHE_ARCHITECTURE
78 ArmCacheArchitecture (
85 OUT ARM_CACHE_INFO
*CacheInfo
102 ArmDataCacheAssociativity (
108 ArmDataCacheLineLength (
114 ArmInstructionCachePresent (
120 ArmInstructionCacheSize (
126 ArmInstructionCacheAssociativity (
132 ArmInstructionCacheLineLength (
150 ArmInvalidateDataCache (
156 ArmCleanInvalidateDataCache (
168 ArmInvalidateInstructionCache (
174 ArmInvalidateDataCacheEntryByMVA (
180 ArmCleanDataCacheEntryByMVA (
186 ArmCleanInvalidateDataCacheEntryByMVA (
198 ArmDisableDataCache (
204 ArmEnableInstructionCache (
210 ArmDisableInstructionCache (
228 ArmEnableInterrupts (
234 ArmDisableInterrupts (
240 ArmGetInterruptState (
252 ArmSetDomainAccessControl (
258 ArmSetTranslationTableBaseAddress (
259 IN VOID
*TranslationTableBase
265 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
266 OUT VOID
**TranslationTableBase OPTIONAL
,
267 OUT UINTN
*TranslationTableSize OPTIONAL
272 ArmSwitchProcessorMode (
273 IN ARM_PROCESSOR_MODE Mode
284 ArmEnableBranchPrediction (
290 ArmDisableBranchPrediction (
294 #endif // __ARM_LIB__