3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 ARM_CACHE_TYPE_WRITE_BACK
,
20 ARM_CACHE_TYPE_UNKNOWN
24 ARM_CACHE_ARCHITECTURE_UNIFIED
,
25 ARM_CACHE_ARCHITECTURE_SEPARATE
,
26 ARM_CACHE_ARCHITECTURE_UNKNOWN
27 } ARM_CACHE_ARCHITECTURE
;
31 ARM_CACHE_ARCHITECTURE Architecture
;
32 BOOLEAN DataCachePresent
;
34 UINTN DataCacheAssociativity
;
35 UINTN DataCacheLineLength
;
36 BOOLEAN InstructionCachePresent
;
37 UINTN InstructionCacheSize
;
38 UINTN InstructionCacheAssociativity
;
39 UINTN InstructionCacheLineLength
;
43 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
,
44 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
45 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
46 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
47 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED
,
48 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK
,
49 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH
,
50 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE
51 } ARM_MEMORY_REGION_ATTRIBUTES
;
57 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
58 } ARM_MEMORY_REGION_DESCRIPTOR
;
60 typedef VOID (*CACHE_OPERATION
)(VOID
);
61 typedef VOID (*LINE_OPERATION
)(UINTN
);
64 ARM_PROCESSOR_MODE_USER
= 0x10,
65 ARM_PROCESSOR_MODE_FIQ
= 0x11,
66 ARM_PROCESSOR_MODE_IRQ
= 0x12,
67 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
68 ARM_PROCESSOR_MODE_ABORT
= 0x17,
69 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
70 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
71 ARM_PROCESSOR_MODE_MASK
= 0x1F
80 ARM_CACHE_ARCHITECTURE
82 ArmCacheArchitecture (
89 OUT ARM_CACHE_INFO
*CacheInfo
106 ArmDataCacheAssociativity (
112 ArmDataCacheLineLength (
118 ArmInstructionCachePresent (
124 ArmInstructionCacheSize (
130 ArmInstructionCacheAssociativity (
136 ArmInstructionCacheLineLength (
160 ArmInvalidateDataCache (
167 ArmCleanInvalidateDataCache (
179 ArmInvalidateInstructionCache (
185 ArmInvalidateDataCacheEntryByMVA (
191 ArmCleanDataCacheEntryByMVA (
197 ArmCleanInvalidateDataCacheEntryByMVA (
209 ArmDisableDataCache (
215 ArmEnableInstructionCache (
221 ArmDisableInstructionCache (
239 ArmDisableCachesAndMmu (
245 ArmEnableInterrupts (
251 ArmDisableInterrupts (
257 ArmGetInterruptState (
287 ArmUpdateTranslationTableEntry (
288 IN VOID
*TranslationTableEntry
,
294 ArmSetDomainAccessControl (
301 IN VOID
*TranslationTableBase
306 ArmGetTTBR0BaseAddress (
313 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
314 OUT VOID
**TranslationTableBase OPTIONAL
,
315 OUT UINTN
*TranslationTableSize OPTIONAL
326 ArmSwitchProcessorMode (
327 IN ARM_PROCESSOR_MODE Mode
338 ArmEnableBranchPrediction (
344 ArmDisableBranchPrediction (
350 ArmDataMemoryBarrier (
356 ArmDataSyncronizationBarrier (
362 ArmInstructionSynchronizationBarrier (
367 #endif // __ARM_LIB__