3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
5 Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
14 #include <Uefi/UefiBaseType.h>
17 #include <Chipset/ArmV7.h>
18 #elif defined (MDE_CPU_AARCH64)
19 #include <Chipset/AArch64.h>
21 #error "Unknown chipset."
24 #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
25 EFI_MEMORY_WT | EFI_MEMORY_WB | \
29 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
31 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
32 * be used in Secure World to distinguished Secure to Non-Secure memory.
35 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
36 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
,
37 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
38 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
,
40 // On some platforms, memory mapped flash region is designed as not supporting
41 // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
43 // Do NOT use below two attributes if you are not sure.
44 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE
,
45 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE
,
47 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
48 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
,
49 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
50 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
51 } ARM_MEMORY_REGION_ATTRIBUTES
;
53 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
56 EFI_PHYSICAL_ADDRESS PhysicalBase
;
57 EFI_VIRTUAL_ADDRESS VirtualBase
;
59 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
60 } ARM_MEMORY_REGION_DESCRIPTOR
;
62 typedef VOID (*CACHE_OPERATION
)(
65 typedef VOID (*LINE_OPERATION
)(
73 ARM_PROCESSOR_MODE_USER
= 0x10,
74 ARM_PROCESSOR_MODE_FIQ
= 0x11,
75 ARM_PROCESSOR_MODE_IRQ
= 0x12,
76 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
77 ARM_PROCESSOR_MODE_ABORT
= 0x17,
78 ARM_PROCESSOR_MODE_HYP
= 0x1A,
79 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
80 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
81 ARM_PROCESSOR_MODE_MASK
= 0x1F
87 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
88 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
89 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
90 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
91 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
92 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
94 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
95 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
96 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
97 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
98 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
99 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
104 #define ARM_CORE_AFF0 0xFF
105 #define ARM_CORE_AFF1 (0xFF << 8)
106 #define ARM_CORE_AFF2 (0xFF << 16)
107 #define ARM_CORE_AFF3 (0xFFULL << 32)
109 #define ARM_CORE_MASK ARM_CORE_AFF0
110 #define ARM_CLUSTER_MASK ARM_CORE_AFF1
111 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
112 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
113 #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
114 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
116 /** Reads the CCSIDR register for the specified cache.
118 @param CSSELR The CSSELR cache selection register value.
120 @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
121 Returns the contents of the CCSIDR register in AARCH32 mode.
128 /** Reads the CCSIDR2 for the specified cache.
130 @param CSSELR The CSSELR cache selection register value
132 @return The contents of the CCSIDR2 register for the specified cache.
139 /** Reads the Cache Level ID (CLIDR) register.
141 @return The contents of the CLIDR_EL1 register.
150 ArmDataCacheLineLength (
156 ArmInstructionCacheLineLength (
162 ArmCacheWritebackGranule (
168 ArmIsArchTimerImplemented (
186 ArmInvalidateDataCache (
192 ArmCleanInvalidateDataCache (
204 ArmInvalidateInstructionCache (
210 ArmInvalidateDataCacheEntryByMVA (
216 ArmCleanDataCacheEntryToPoUByMVA (
222 ArmInvalidateInstructionCacheEntryToPoUByMVA (
228 ArmCleanDataCacheEntryByMVA (
234 ArmCleanInvalidateDataCacheEntryByMVA (
246 ArmDisableDataCache (
252 ArmEnableInstructionCache (
258 ArmDisableInstructionCache (
276 ArmEnableCachesAndMmu (
282 ArmDisableCachesAndMmu (
288 ArmEnableInterrupts (
294 ArmDisableInterrupts (
300 ArmGetInterruptState (
306 ArmEnableAsynchronousAbort (
312 ArmDisableAsynchronousAbort (
347 * Invalidate Data and Instruction TLBs
357 ArmUpdateTranslationTableEntry (
358 IN VOID
*TranslationTableEntry
,
364 ArmSetDomainAccessControl (
371 IN VOID
*TranslationTableBase
382 ArmGetTTBR0BaseAddress (
394 ArmEnableBranchPrediction (
400 ArmDisableBranchPrediction (
418 ArmDataMemoryBarrier (
424 ArmDataSynchronizationBarrier (
430 ArmInstructionSynchronizationBarrier (
520 Get the Secure Configuration Register value
522 @return Value read from the Secure Configuration Register
532 Set the Secure Configuration Register
534 @param Value Value to write to the Secure Configuration Register
552 IN UINT32 VectorMonitorBase
576 IN UINTN HypModeVectorBase
580 // Helper functions for accessing CPU ACTLR
603 ArmUnsetCpuActlrBit (
608 // Accessors for the architected generic timer registers
611 #define ARM_ARCH_TIMER_ENABLE (1 << 0)
612 #define ARM_ARCH_TIMER_IMASK (1 << 1)
613 #define ARM_ARCH_TIMER_ISTATUS (1 << 2)
737 ArmGetPhysicalAddressBits (
742 /// ID Register Helper functions
746 Check whether the CPU supports the GIC system register interface (any version)
748 @return Whether GIC System Register Interface is supported
753 ArmHasGicSystemRegisters (
757 /** Checks if CCIDX is implemented.
759 @retval TRUE CCIDX is implemented.
760 @retval FALSE CCIDX is not implemented.
770 /// AArch32-only ID Register Helper functions
774 Check whether the CPU supports the Security extensions
776 @return Whether the Security extensions are implemented
781 ArmHasSecurityExtensions (
785 #endif // MDE_CPU_ARM