3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Chipset/AArch64.h>
18 #include <Library/ArmLib.h>
19 #include <Library/BaseLib.h>
20 #include <Library/IoLib.h>
21 #include "AArch64Lib.h"
22 #include "ArmLibPrivate.h"
30 return ARM_CACHE_TYPE_WRITE_BACK
;
33 ARM_CACHE_ARCHITECTURE
35 ArmCacheArchitecture (
39 UINT32 CLIDR
= ReadCLIDR ();
41 return (ARM_CACHE_ARCHITECTURE
)CLIDR
; // BugBug Fix Me
50 UINT32 CLIDR
= ReadCLIDR ();
52 if ((CLIDR
& 0x2) == 0x2) {
53 // Instruction cache exists
56 if ((CLIDR
& 0x7) == 0x4) {
73 UINT32 CCSIDR
= ReadCCSIDR (0);
75 LineSize
= (1 << ((CCSIDR
& 0x7) + 2));
76 Associativity
= ((CCSIDR
>> 3) & 0x3ff) + 1;
77 NumSets
= ((CCSIDR
>> 13) & 0x7fff) + 1;
79 // LineSize is in words (4 byte chunks)
80 return NumSets
* Associativity
* LineSize
* 4;
85 ArmDataCacheAssociativity (
89 UINT32 CCSIDR
= ReadCCSIDR (0);
91 return ((CCSIDR
>> 3) & 0x3ff) + 1;
99 UINT32 CCSIDR
= ReadCCSIDR (0);
101 return ((CCSIDR
>> 13) & 0x7fff) + 1;
106 ArmDataCacheLineLength (
110 UINT32 CCSIDR
= ReadCCSIDR (0) & 7;
112 // * 4 converts to bytes
113 return (1 << (CCSIDR
+ 2)) * 4;
118 ArmInstructionCachePresent (
122 UINT32 CLIDR
= ReadCLIDR ();
124 if ((CLIDR
& 1) == 1) {
125 // Instruction cache exists
128 if ((CLIDR
& 0x7) == 0x4) {
138 ArmInstructionCacheSize (
143 UINT32 Associativity
;
145 UINT32 CCSIDR
= ReadCCSIDR (1);
147 LineSize
= (1 << ((CCSIDR
& 0x7) + 2));
148 Associativity
= ((CCSIDR
>> 3) & 0x3ff) + 1;
149 NumSets
= ((CCSIDR
>> 13) & 0x7fff) + 1;
151 // LineSize is in words (4 byte chunks)
152 return NumSets
* Associativity
* LineSize
* 4;
157 ArmInstructionCacheAssociativity (
161 UINT32 CCSIDR
= ReadCCSIDR (1);
163 return ((CCSIDR
>> 3) & 0x3ff) + 1;
168 ArmInstructionCacheSets (
172 UINT32 CCSIDR
= ReadCCSIDR (1);
174 return ((CCSIDR
>> 13) & 0x7fff) + 1;
179 ArmInstructionCacheLineLength (
183 UINT32 CCSIDR
= ReadCCSIDR (1) & 7;
185 // * 4 converts to bytes
186 return (1 << (CCSIDR
+ 2)) * 4;
191 AArch64DataCacheOperation (
192 IN AARCH64_CACHE_OPERATION DataCacheOperation
195 UINTN SavedInterruptState
;
197 SavedInterruptState
= ArmGetInterruptState ();
198 ArmDisableInterrupts();
200 AArch64AllDataCachesOperation (DataCacheOperation
);
202 ArmDrainWriteBuffer ();
204 if (SavedInterruptState
) {
205 ArmEnableInterrupts ();
211 AArch64PoUDataCacheOperation (
212 IN AARCH64_CACHE_OPERATION DataCacheOperation
215 UINTN SavedInterruptState
;
217 SavedInterruptState
= ArmGetInterruptState ();
218 ArmDisableInterrupts ();
220 AArch64PerformPoUDataCacheOperation (DataCacheOperation
);
222 ArmDrainWriteBuffer ();
224 if (SavedInterruptState
) {
225 ArmEnableInterrupts ();
231 ArmInvalidateDataCache (
235 AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay
);
240 ArmCleanInvalidateDataCache (
244 AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay
);
253 AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay
);
258 ArmCleanDataCacheToPoU (
262 AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay
);