ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c

   1 /** @file
   2 *  File managing the MMU for ARMv8 architecture
   3 *
   4 *  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15
  16 #include <Uefi.h>
  17 #include <Chipset/AArch64.h>
  18 #include <Library/BaseMemoryLib.h>
  19 #include <Library/MemoryAllocationLib.h>
  20 #include <Library/ArmLib.h>
  21 #include <Library/BaseLib.h>
  22 #include <Library/DebugLib.h>
  23 #include "AArch64Lib.h"
  24 #include "ArmLibPrivate.h"
  25
  26 // We use this index definition to define an invalid block entry
  27 #define TT_ATTR_INDX_INVALID    ((UINT32)~0)
  28
  29 STATIC
  30 UINT64
  31 ArmMemoryAttributeToPageAttribute (
  32   IN ARM_MEMORY_REGION_ATTRIBUTES  Attributes
  33   )
  34 {
  35   switch (Attributes) {
  36   case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
  37     return TT_ATTR_INDX_MEMORY_WRITE_BACK;
  38   case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
  39     return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
  40   case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
  41     return TT_ATTR_INDX_DEVICE_MEMORY;
  42   case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
  43     return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
  44   case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
  45     return TT_ATTR_INDX_MEMORY_WRITE_BACK;
  46   case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
  47     return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
  48   case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
  49     return TT_ATTR_INDX_DEVICE_MEMORY;
  50   case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
  51     return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
  52   default:
  53     ASSERT(0);
  54     return TT_ATTR_INDX_DEVICE_MEMORY;
  55   }
  56 }
  57
  58 UINT64
  59 PageAttributeToGcdAttribute (
  60   IN UINT64 PageAttributes
  61   )
  62 {
  63   UINT64  GcdAttributes;
  64
  65   switch (PageAttributes & TT_ATTR_INDX_MASK) {
  66   case TT_ATTR_INDX_DEVICE_MEMORY:
  67     GcdAttributes = EFI_MEMORY_UC;
  68     break;
  69   case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
  70     GcdAttributes = EFI_MEMORY_WC;
  71     break;
  72   case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
  73     GcdAttributes = EFI_MEMORY_WT;
  74     break;
  75   case TT_ATTR_INDX_MEMORY_WRITE_BACK:
  76     GcdAttributes = EFI_MEMORY_WB;
  77     break;
  78   default:
  79     DEBUG ((EFI_D_ERROR, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes));
  80     ASSERT (0);
  81     // The Global Coherency Domain (GCD) value is defined as a bit set.
  82     // Returning 0 means no attribute has been set.
  83     GcdAttributes = 0;
  84   }
  85
  86   // Determine protection attributes
  87   if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
  88     // Read only cases map to write-protect
  89     GcdAttributes |= EFI_MEMORY_WP;
  90   }
  91
  92   // Process eXecute Never attribute
  93   if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0 ) {
  94     GcdAttributes |= EFI_MEMORY_XP;
  95   }
  96
  97   return GcdAttributes;
  98 }
  99
 100 UINT64
 101 GcdAttributeToPageAttribute (
 102   IN UINT64 GcdAttributes
 103   )
 104 {
 105   UINT64  PageAttributes;
 106
 107   switch (GcdAttributes & 0xFF) {
 108   case EFI_MEMORY_UC:
 109     PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
 110     break;
 111   case EFI_MEMORY_WC:
 112     PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
 113     break;
 114   case EFI_MEMORY_WT:
 115     PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
 116     break;
 117   case EFI_MEMORY_WB:
 118     PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK;
 119     break;
 120   default:
 121     DEBUG ((EFI_D_ERROR, "GcdAttributeToPageAttribute: 0x%X attributes is not supported.\n", GcdAttributes));
 122     ASSERT (0);
 123     // If no match has been found then we mark the memory as device memory.
 124     // The only side effect of using device memory should be a slow down in the performance.
 125     PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
 126   }
 127
 128   // Determine protection attributes
 129   if (GcdAttributes & EFI_MEMORY_WP) {
 130     // Read only cases map to write-protect
 131     PageAttributes |= TT_AP_RO_RO;
 132   }
 133
 134   // Process eXecute Never attribute
 135   if (GcdAttributes & EFI_MEMORY_XP) {
 136     PageAttributes |= (TT_PXN_MASK | TT_UXN_MASK);
 137   }
 138
 139   return PageAttributes;
 140 }
 141
 142 ARM_MEMORY_REGION_ATTRIBUTES
 143 GcdAttributeToArmAttribute (
 144   IN UINT64 GcdAttributes
 145   )
 146 {
 147   switch (GcdAttributes & 0xFF) {
 148   case EFI_MEMORY_UC:
 149     return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 150   case EFI_MEMORY_WC:
 151     return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
 152   case EFI_MEMORY_WT:
 153     return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
 154   case EFI_MEMORY_WB:
 155     return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
 156   default:
 157     DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes));
 158     ASSERT (0);
 159     return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 160   }
 161 }
 162
 163 // Describe the T0SZ values for each translation table level
 164 typedef struct {
 165   UINTN     MinT0SZ;
 166   UINTN     MaxT0SZ;
 167   UINTN     LargestT0SZ; // Generally (MaxT0SZ == LargestT0SZ) but at the Level3 Table
 168                          // the MaxT0SZ is not at the boundary of the table
 169 } T0SZ_DESCRIPTION_PER_LEVEL;
 170
 171 // Map table for the corresponding Level of Table
 172 STATIC CONST T0SZ_DESCRIPTION_PER_LEVEL T0SZPerTableLevel[] = {
 173     { 16, 24, 24 }, // Table Level 0
 174     { 25, 33, 33 }, // Table Level 1
 175     { 34, 39, 42 }  // Table Level 2
 176 };
 177
 178 VOID
 179 GetRootTranslationTableInfo (
 180   IN UINTN     T0SZ,
 181   OUT UINTN   *TableLevel,
 182   OUT UINTN   *TableEntryCount
 183   )
 184 {
 185   UINTN Index;
 186
 187   // Identify the level of the root table from the given T0SZ
 188   for (Index = 0; Index < sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL); Index++) {
 189     if (T0SZ <= T0SZPerTableLevel[Index].MaxT0SZ) {
 190       break;
 191     }
 192   }
 193
 194   // If we have not found the corresponding maximum T0SZ then we use the last one
 195   if (Index == sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL)) {
 196     Index--;
 197   }
 198
 199   // Get the level of the root table
 200   if (TableLevel) {
 201     *TableLevel = Index;
 202   }
 203
 204   // The Size of the Table is 2^(T0SZ-LargestT0SZ)
 205   if (TableEntryCount) {
 206     *TableEntryCount = 1 << (T0SZPerTableLevel[Index].LargestT0SZ - T0SZ + 1);
 207   }
 208 }
 209
 210 STATIC
 211 VOID
 212 LookupAddresstoRootTable (
 213   IN  UINT64  MaxAddress,
 214   OUT UINTN  *T0SZ,
 215   OUT UINTN  *TableEntryCount
 216   )
 217 {
 218   UINTN TopBit;
 219
 220   // Check the parameters are not NULL
 221   ASSERT ((T0SZ != NULL) && (TableEntryCount != NULL));
 222
 223   // Look for the highest bit set in MaxAddress
 224   for (TopBit = 63; TopBit != 0; TopBit--) {
 225     if ((1ULL << TopBit) & MaxAddress) {
 226       // MaxAddress top bit is found
 227       TopBit = TopBit + 1;
 228       break;
 229     }
 230   }
 231   ASSERT (TopBit != 0);
 232
 233   // Calculate T0SZ from the top bit of the MaxAddress
 234   *T0SZ = 64 - TopBit;
 235
 236   // Get the Table info from T0SZ
 237   GetRootTranslationTableInfo (*T0SZ, NULL, TableEntryCount);
 238 }
 239
 240 STATIC
 241 UINT64*
 242 GetBlockEntryListFromAddress (
 243   IN  UINT64       *RootTable,
 244   IN  UINT64        RegionStart,
 245   OUT UINTN        *TableLevel,
 246   IN OUT UINT64    *BlockEntrySize,
 247   IN OUT UINT64   **LastBlockEntry
 248   )
 249 {
 250   UINTN   RootTableLevel;
 251   UINTN   RootTableEntryCount;
 252   UINT64 *TranslationTable;
 253   UINT64 *BlockEntry;
 254   UINT64  BlockEntryAddress;
 255   UINTN   BaseAddressAlignment;
 256   UINTN   PageLevel;
 257   UINTN   Index;
 258   UINTN   IndexLevel;
 259   UINTN   T0SZ;
 260   UINT64  Attributes;
 261   UINT64  TableAttributes;
 262
 263   // Initialize variable
 264   BlockEntry = NULL;
 265
 266   // Ensure the parameters are valid
 267   ASSERT (TableLevel && BlockEntrySize && LastBlockEntry);
 268
 269   // Ensure the Region is aligned on 4KB boundary
 270   ASSERT ((RegionStart & (SIZE_4KB - 1)) == 0);
 271
 272   // Ensure the required size is aligned on 4KB boundary
 273   ASSERT ((*BlockEntrySize & (SIZE_4KB - 1)) == 0);
 274
 275   //
 276   // Calculate LastBlockEntry from T0SZ - this is the last block entry of the root Translation table
 277   //
 278   T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
 279   // Get the Table info from T0SZ
 280   GetRootTranslationTableInfo (T0SZ, &RootTableLevel, &RootTableEntryCount);
 281   // The last block of the root table depends on the number of entry in this table
 282   *LastBlockEntry = (UINT64*)((UINTN)RootTable + ((RootTableEntryCount - 1) * sizeof(UINT64)));
 283
 284   // If the start address is 0x0 then we use the size of the region to identify the alignment
 285   if (RegionStart == 0) {
 286     // Identify the highest possible alignment for the Region Size
 287     for (BaseAddressAlignment = 0; BaseAddressAlignment < 64; BaseAddressAlignment++) {
 288       if ((1 << BaseAddressAlignment) & *BlockEntrySize) {
 289         break;
 290       }
 291     }
 292   } else {
 293     // Identify the highest possible alignment for the Base Address
 294     for (BaseAddressAlignment = 0; BaseAddressAlignment < 64; BaseAddressAlignment++) {
 295       if ((1 << BaseAddressAlignment) & RegionStart) {
 296         break;
 297       }
 298     }
 299   }
 300
 301   // Identify the Page Level the RegionStart must belongs to
 302   PageLevel = 3 - ((BaseAddressAlignment - 12) / 9);
 303
 304   // If the required size is smaller than the current block size then we need to go to the page bellow.
 305   if (*BlockEntrySize < TT_ADDRESS_AT_LEVEL(PageLevel)) {
 306     // It does not fit so we need to go a page level above
 307     PageLevel++;
 308   }
 309
 310   // Expose the found PageLevel to the caller
 311   *TableLevel = PageLevel;
 312
 313   // Now, we have the Table Level we can get the Block Size associated to this table
 314   *BlockEntrySize = TT_ADDRESS_AT_LEVEL(PageLevel);
 315
 316   //
 317   // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries
 318   //
 319
 320   TranslationTable = RootTable;
 321   for (IndexLevel = RootTableLevel; IndexLevel <= PageLevel; IndexLevel++) {
 322     BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel, RegionStart);
 323
 324     if ((IndexLevel != 3) && ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {
 325       // Go to the next table
 326       TranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
 327
 328       // If we are at the last level then update the output
 329       if (IndexLevel == PageLevel) {
 330         // And get the appropriate BlockEntry at the next level
 331         BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel + 1, RegionStart);
 332
 333         // Set the last block for this new table
 334         *LastBlockEntry = (UINT64*)((UINTN)TranslationTable + ((TT_ENTRY_COUNT - 1) * sizeof(UINT64)));
 335       }
 336     } else if ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) {
 337       // If we are not at the last level then we need to split this BlockEntry
 338       if (IndexLevel != PageLevel) {
 339         // Retrieve the attributes from the block entry
 340         Attributes = *BlockEntry & TT_ATTRIBUTES_MASK;
 341
 342         // Convert the block entry attributes into Table descriptor attributes
 343         TableAttributes = TT_TABLE_AP_NO_PERMISSION;
 344         if (Attributes & TT_PXN_MASK) {
 345           TableAttributes = TT_TABLE_PXN;
 346         }
 347         if (Attributes & TT_UXN_MASK) {
 348           TableAttributes = TT_TABLE_XN;
 349         }
 350         if (Attributes & TT_NS) {
 351           TableAttributes = TT_TABLE_NS;
 352         }
 353
 354         // Get the address corresponding at this entry
 355         BlockEntryAddress = RegionStart;
 356         BlockEntryAddress = BlockEntryAddress >> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
 357         // Shift back to right to set zero before the effective address
 358         BlockEntryAddress = BlockEntryAddress << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
 359
 360         // Set the correct entry type
 361         if (IndexLevel + 1 == 3) {
 362           Attributes |= TT_TYPE_BLOCK_ENTRY_LEVEL3;
 363         } else {
 364           Attributes |= TT_TYPE_BLOCK_ENTRY;
 365         }
 366
 367         // Create a new translation table
 368         TranslationTable = (UINT64*)AllocatePages (EFI_SIZE_TO_PAGES((TT_ENTRY_COUNT * sizeof(UINT64)) + TT_ALIGNMENT_DESCRIPTION_TABLE));
 369         if (TranslationTable == NULL) {
 370           return NULL;
 371         }
 372         TranslationTable = (UINT64*)((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
 373
 374         // Fill the new BlockEntry with the TranslationTable
 375         *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY;
 376         // Update the last block entry with the newly created translation table
 377         *LastBlockEntry = (UINT64*)((UINTN)TranslationTable + ((TT_ENTRY_COUNT - 1) * sizeof(UINT64)));
 378
 379         // Populate the newly created lower level table
 380         BlockEntry = TranslationTable;
 381         for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
 382           *BlockEntry = Attributes | (BlockEntryAddress + (Index << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel + 1)));
 383           BlockEntry++;
 384         }
 385         // Block Entry points at the beginning of the Translation Table
 386         BlockEntry = TranslationTable;
 387       }
 388     } else {
 389       // Case of Invalid Entry and we are at a page level above of the one targetted.
 390       if (IndexLevel != PageLevel) {
 391         // Create a new translation table
 392         TranslationTable = (UINT64*)AllocatePages (EFI_SIZE_TO_PAGES((TT_ENTRY_COUNT * sizeof(UINT64)) + TT_ALIGNMENT_DESCRIPTION_TABLE));
 393         if (TranslationTable == NULL) {
 394           return NULL;
 395         }
 396         TranslationTable = (UINT64*)((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
 397
 398         ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64));
 399
 400         // Fill the new BlockEntry with the TranslationTable
 401         *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;
 402       }
 403     }
 404   }
 405
 406   return BlockEntry;
 407 }
 408
 409 STATIC
 410 RETURN_STATUS
 411 FillTranslationTable (
 412   IN  UINT64                        *RootTable,
 413   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
 414   )
 415 {
 416   UINT64  Attributes;
 417   UINT32  Type;
 418   UINT64  RegionStart;
 419   UINT64  RemainingRegionLength;
 420   UINT64 *BlockEntry;
 421   UINT64 *LastBlockEntry;
 422   UINT64  BlockEntrySize;
 423   UINTN   TableLevel;
 424
 425   // Ensure the Length is aligned on 4KB boundary
 426   ASSERT ((MemoryRegion->Length > 0) && ((MemoryRegion->Length & (SIZE_4KB - 1)) == 0));
 427
 428   // Variable initialization
 429   Attributes = ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF;
 430   RemainingRegionLength = MemoryRegion->Length;
 431   RegionStart = MemoryRegion->VirtualBase;
 432
 433   do {
 434     // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor
 435     // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
 436     BlockEntrySize = RemainingRegionLength;
 437     BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);
 438     if (BlockEntry == NULL) {
 439       // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables
 440       return RETURN_OUT_OF_RESOURCES;
 441     }
 442
 443     if (TableLevel != 3) {
 444       Type = TT_TYPE_BLOCK_ENTRY;
 445     } else {
 446       Type = TT_TYPE_BLOCK_ENTRY_LEVEL3;
 447     }
 448
 449     do {
 450       // Fill the Block Entry with attribute and output block address
 451       *BlockEntry = (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type;
 452
 453       // Go to the next BlockEntry
 454       RegionStart += BlockEntrySize;
 455       RemainingRegionLength -= BlockEntrySize;
 456       BlockEntry++;
 457     } while ((RemainingRegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry));
 458   } while (RemainingRegionLength != 0);
 459
 460   return RETURN_SUCCESS;
 461 }
 462
 463 RETURN_STATUS
 464 SetMemoryAttributes (
 465   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 466   IN UINT64                    Length,
 467   IN UINT64                    Attributes,
 468   IN EFI_PHYSICAL_ADDRESS      VirtualMask
 469   )
 470 {
 471   RETURN_STATUS                Status;
 472   ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion;
 473   UINT64                      *TranslationTable;
 474
 475   MemoryRegion.PhysicalBase = BaseAddress;
 476   MemoryRegion.VirtualBase = BaseAddress;
 477   MemoryRegion.Length = Length;
 478   MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes);
 479
 480   TranslationTable = ArmGetTTBR0BaseAddress ();
 481
 482   Status = FillTranslationTable (TranslationTable, &MemoryRegion);
 483   if (RETURN_ERROR (Status)) {
 484     return Status;
 485   }
 486
 487   // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
 488   // flush and invalidate pages
 489   ArmCleanInvalidateDataCache ();
 490
 491   ArmInvalidateInstructionCache ();
 492
 493   // Invalidate all TLB entries so changes are synced
 494   ArmInvalidateTlb ();
 495
 496   return RETURN_SUCCESS;
 497 }
 498
 499 RETURN_STATUS
 500 EFIAPI
 501 ArmConfigureMmu (
 502   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 503   OUT VOID                         **TranslationTableBase OPTIONAL,
 504   OUT UINTN                         *TranslationTableSize OPTIONAL
 505   )
 506 {
 507   VOID*                         TranslationTable;
 508   UINTN                         TranslationTablePageCount;
 509   UINT32                        TranslationTableAttribute;
 510   ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry;
 511   UINT64                        MaxAddress;
 512   UINT64                        TopAddress;
 513   UINTN                         T0SZ;
 514   UINTN                         RootTableEntryCount;
 515   UINT64                        TCR;
 516   RETURN_STATUS                 Status;
 517
 518   ASSERT (MemoryTable != NULL);
 519
 520   // Identify the highest address of the memory table
 521   MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1;
 522   MemoryTableEntry = MemoryTable;
 523   while (MemoryTableEntry->Length != 0) {
 524     TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1;
 525     if (TopAddress > MaxAddress) {
 526       MaxAddress = TopAddress;
 527     }
 528     MemoryTableEntry++;
 529   }
 530
 531   // Lookup the Table Level to get the information
 532   LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);
 533
 534   //
 535   // Set TCR that allows us to retrieve T0SZ in the subsequent functions
 536   //
 537   if ((ArmReadCurrentEL () == AARCH64_EL2) || (ArmReadCurrentEL () == AARCH64_EL3)) {
 538     //Note: Bits 23 and 31 are reserved bits in TCR_EL2 and TCR_EL3
 539     TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
 540
 541     // Set the Physical Address Size using MaxAddress
 542     if (MaxAddress < SIZE_4GB) {
 543       TCR |= TCR_PS_4GB;
 544     } else if (MaxAddress < SIZE_64GB) {
 545       TCR |= TCR_PS_64GB;
 546     } else if (MaxAddress < SIZE_1TB) {
 547       TCR |= TCR_PS_1TB;
 548     } else if (MaxAddress < SIZE_4TB) {
 549       TCR |= TCR_PS_4TB;
 550     } else if (MaxAddress < SIZE_16TB) {
 551       TCR |= TCR_PS_16TB;
 552     } else if (MaxAddress < SIZE_256TB) {
 553       TCR |= TCR_PS_256TB;
 554     } else {
 555       DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU support.\n", MaxAddress));
 556       ASSERT (0); // Bigger than 48-bit memory space are not supported
 557       return RETURN_UNSUPPORTED;
 558     }
 559   } else {
 560     ASSERT (0); // Bigger than 48-bit memory space are not supported
 561     return RETURN_UNSUPPORTED;
 562   }
 563
 564   // Set TCR
 565   ArmSetTCR (TCR);
 566
 567   // Allocate pages for translation table
 568   TranslationTablePageCount = EFI_SIZE_TO_PAGES((RootTableEntryCount * sizeof(UINT64)) + TT_ALIGNMENT_DESCRIPTION_TABLE);
 569   TranslationTable = AllocatePages (TranslationTablePageCount);
 570   if (TranslationTable == NULL) {
 571     return RETURN_OUT_OF_RESOURCES;
 572   }
 573   TranslationTable = (VOID*)((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
 574   // We set TTBR0 just after allocating the table to retrieve its location from the subsequent
 575   // functions without needing to pass this value across the functions. The MMU is only enabled
 576   // after the translation tables are populated.
 577   ArmSetTTBR0 (TranslationTable);
 578
 579   if (TranslationTableBase != NULL) {
 580     *TranslationTableBase = TranslationTable;
 581   }
 582
 583   if (TranslationTableSize != NULL) {
 584     *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);
 585   }
 586
 587   ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
 588
 589   // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
 590   ArmDisableMmu ();
 591   ArmDisableDataCache ();
 592   ArmDisableInstructionCache ();
 593
 594   // Make sure nothing sneaked into the cache
 595   ArmCleanInvalidateDataCache ();
 596   ArmInvalidateInstructionCache ();
 597
 598   TranslationTableAttribute = TT_ATTR_INDX_INVALID;
 599   while (MemoryTable->Length != 0) {
 600     // Find the memory attribute for the Translation Table
 601     if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) &&
 602         ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
 603       TranslationTableAttribute = MemoryTable->Attributes;
 604     }
 605
 606     Status = FillTranslationTable (TranslationTable, MemoryTable);
 607     if (RETURN_ERROR (Status)) {
 608       goto FREE_TRANSLATION_TABLE;
 609     }
 610     MemoryTable++;
 611   }
 612
 613   // Translate the Memory Attributes into Translation Table Register Attributes
 614   if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
 615       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
 616     TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE | TCR_RGN_INNER_NON_CACHEABLE;
 617   } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
 618       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
 619     TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC | TCR_RGN_INNER_WRITE_BACK_ALLOC;
 620   } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
 621       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
 622     TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH | TCR_RGN_INNER_WRITE_THROUGH;
 623   } else {
 624     // If we failed to find a mapping that contains the root translation table then it probably means the translation table
 625     // is not mapped in the given memory map.
 626     ASSERT (0);
 627     Status = RETURN_UNSUPPORTED;
 628     goto FREE_TRANSLATION_TABLE;
 629   }
 630
 631   ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |                      // mapped to EFI_MEMORY_UC
 632               MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC
 633               MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT
 634               MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK));       // mapped to EFI_MEMORY_WB
 635
 636   ArmDisableAlignmentCheck ();
 637   ArmEnableInstructionCache ();
 638   ArmEnableDataCache ();
 639
 640   ArmEnableMmu ();
 641   return RETURN_SUCCESS;
 642
 643 FREE_TRANSLATION_TABLE:
 644   FreePages (TranslationTable, TranslationTablePageCount);
 645   return Status;
 646 }