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[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Mmu.c
1 /** @file
2 * File managing the MMU for ARMv8 architecture
3 *
4 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16 #include <Uefi.h>
17 #include <Chipset/AArch64.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/MemoryAllocationLib.h>
20 #include <Library/ArmLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/DebugLib.h>
23 #include "AArch64Lib.h"
24 #include "ArmLibPrivate.h"
25
26 // We use this index definition to define an invalid block entry
27 #define TT_ATTR_INDX_INVALID ((UINT32)~0)
28
29 STATIC
30 UINT64
31 ArmMemoryAttributeToPageAttribute (
32 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
33 )
34 {
35 switch (Attributes) {
36 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
37 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
38 return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
39
40 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
41 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
42 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
43
44 // Uncached and device mappings are treated as outer shareable by default,
45 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
46 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
47 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
48
49 default:
50 ASSERT(0);
51 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
52 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
53 if (ArmReadCurrentEL () == AARCH64_EL2)
54 return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
55 else
56 return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
57 }
58 }
59
60 UINT64
61 PageAttributeToGcdAttribute (
62 IN UINT64 PageAttributes
63 )
64 {
65 UINT64 GcdAttributes;
66
67 switch (PageAttributes & TT_ATTR_INDX_MASK) {
68 case TT_ATTR_INDX_DEVICE_MEMORY:
69 GcdAttributes = EFI_MEMORY_UC;
70 break;
71 case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
72 GcdAttributes = EFI_MEMORY_WC;
73 break;
74 case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
75 GcdAttributes = EFI_MEMORY_WT;
76 break;
77 case TT_ATTR_INDX_MEMORY_WRITE_BACK:
78 GcdAttributes = EFI_MEMORY_WB;
79 break;
80 default:
81 DEBUG ((EFI_D_ERROR, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes));
82 ASSERT (0);
83 // The Global Coherency Domain (GCD) value is defined as a bit set.
84 // Returning 0 means no attribute has been set.
85 GcdAttributes = 0;
86 }
87
88 // Determine protection attributes
89 if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
90 // Read only cases map to write-protect
91 GcdAttributes |= EFI_MEMORY_WP;
92 }
93
94 // Process eXecute Never attribute
95 if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0 ) {
96 GcdAttributes |= EFI_MEMORY_XP;
97 }
98
99 return GcdAttributes;
100 }
101
102 ARM_MEMORY_REGION_ATTRIBUTES
103 GcdAttributeToArmAttribute (
104 IN UINT64 GcdAttributes
105 )
106 {
107 switch (GcdAttributes & 0xFF) {
108 case EFI_MEMORY_UC:
109 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
110 case EFI_MEMORY_WC:
111 return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
112 case EFI_MEMORY_WT:
113 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
114 case EFI_MEMORY_WB:
115 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
116 default:
117 DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes));
118 ASSERT (0);
119 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
120 }
121 }
122
123 // Describe the T0SZ values for each translation table level
124 typedef struct {
125 UINTN MinT0SZ;
126 UINTN MaxT0SZ;
127 UINTN LargestT0SZ; // Generally (MaxT0SZ == LargestT0SZ) but at the Level3 Table
128 // the MaxT0SZ is not at the boundary of the table
129 } T0SZ_DESCRIPTION_PER_LEVEL;
130
131 // Map table for the corresponding Level of Table
132 STATIC CONST T0SZ_DESCRIPTION_PER_LEVEL T0SZPerTableLevel[] = {
133 { 16, 24, 24 }, // Table Level 0
134 { 25, 33, 33 }, // Table Level 1
135 { 34, 39, 42 } // Table Level 2
136 };
137
138 VOID
139 GetRootTranslationTableInfo (
140 IN UINTN T0SZ,
141 OUT UINTN *TableLevel,
142 OUT UINTN *TableEntryCount
143 )
144 {
145 UINTN Index;
146
147 // Identify the level of the root table from the given T0SZ
148 for (Index = 0; Index < sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL); Index++) {
149 if (T0SZ <= T0SZPerTableLevel[Index].MaxT0SZ) {
150 break;
151 }
152 }
153
154 // If we have not found the corresponding maximum T0SZ then we use the last one
155 if (Index == sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL)) {
156 Index--;
157 }
158
159 // Get the level of the root table
160 if (TableLevel) {
161 *TableLevel = Index;
162 }
163
164 // The Size of the Table is 2^(T0SZ-LargestT0SZ)
165 if (TableEntryCount) {
166 *TableEntryCount = 1 << (T0SZPerTableLevel[Index].LargestT0SZ - T0SZ + 1);
167 }
168 }
169
170 STATIC
171 VOID
172 ReplaceLiveEntry (
173 IN UINT64 *Entry,
174 IN UINT64 Value
175 )
176 {
177 if (!ArmMmuEnabled ()) {
178 *Entry = Value;
179 } else {
180 ArmReplaceLiveTranslationEntry (Entry, Value);
181 }
182 }
183
184 STATIC
185 VOID
186 LookupAddresstoRootTable (
187 IN UINT64 MaxAddress,
188 OUT UINTN *T0SZ,
189 OUT UINTN *TableEntryCount
190 )
191 {
192 UINTN TopBit;
193
194 // Check the parameters are not NULL
195 ASSERT ((T0SZ != NULL) && (TableEntryCount != NULL));
196
197 // Look for the highest bit set in MaxAddress
198 for (TopBit = 63; TopBit != 0; TopBit--) {
199 if ((1ULL << TopBit) & MaxAddress) {
200 // MaxAddress top bit is found
201 TopBit = TopBit + 1;
202 break;
203 }
204 }
205 ASSERT (TopBit != 0);
206
207 // Calculate T0SZ from the top bit of the MaxAddress
208 *T0SZ = 64 - TopBit;
209
210 // Get the Table info from T0SZ
211 GetRootTranslationTableInfo (*T0SZ, NULL, TableEntryCount);
212 }
213
214 STATIC
215 UINT64*
216 GetBlockEntryListFromAddress (
217 IN UINT64 *RootTable,
218 IN UINT64 RegionStart,
219 OUT UINTN *TableLevel,
220 IN OUT UINT64 *BlockEntrySize,
221 OUT UINT64 **LastBlockEntry
222 )
223 {
224 UINTN RootTableLevel;
225 UINTN RootTableEntryCount;
226 UINT64 *TranslationTable;
227 UINT64 *BlockEntry;
228 UINT64 *SubTableBlockEntry;
229 UINT64 BlockEntryAddress;
230 UINTN BaseAddressAlignment;
231 UINTN PageLevel;
232 UINTN Index;
233 UINTN IndexLevel;
234 UINTN T0SZ;
235 UINT64 Attributes;
236 UINT64 TableAttributes;
237
238 // Initialize variable
239 BlockEntry = NULL;
240
241 // Ensure the parameters are valid
242 if (!(TableLevel && BlockEntrySize && LastBlockEntry)) {
243 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
244 return NULL;
245 }
246
247 // Ensure the Region is aligned on 4KB boundary
248 if ((RegionStart & (SIZE_4KB - 1)) != 0) {
249 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
250 return NULL;
251 }
252
253 // Ensure the required size is aligned on 4KB boundary and not 0
254 if ((*BlockEntrySize & (SIZE_4KB - 1)) != 0 || *BlockEntrySize == 0) {
255 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
256 return NULL;
257 }
258
259 T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
260 // Get the Table info from T0SZ
261 GetRootTranslationTableInfo (T0SZ, &RootTableLevel, &RootTableEntryCount);
262
263 // If the start address is 0x0 then we use the size of the region to identify the alignment
264 if (RegionStart == 0) {
265 // Identify the highest possible alignment for the Region Size
266 BaseAddressAlignment = LowBitSet64 (*BlockEntrySize);
267 } else {
268 // Identify the highest possible alignment for the Base Address
269 BaseAddressAlignment = LowBitSet64 (RegionStart);
270 }
271
272 // Identify the Page Level the RegionStart must belong to. Note that PageLevel
273 // should be at least 1 since block translations are not supported at level 0
274 PageLevel = MAX (3 - ((BaseAddressAlignment - 12) / 9), 1);
275
276 // If the required size is smaller than the current block size then we need to go to the page below.
277 // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment
278 // of the allocation size
279 while (*BlockEntrySize < TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel)) {
280 // It does not fit so we need to go a page level above
281 PageLevel++;
282 }
283
284 //
285 // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries
286 //
287
288 TranslationTable = RootTable;
289 for (IndexLevel = RootTableLevel; IndexLevel <= PageLevel; IndexLevel++) {
290 BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel, RegionStart);
291
292 if ((IndexLevel != 3) && ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {
293 // Go to the next table
294 TranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
295
296 // If we are at the last level then update the last level to next level
297 if (IndexLevel == PageLevel) {
298 // Enter the next level
299 PageLevel++;
300 }
301 } else if ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) {
302 // If we are not at the last level then we need to split this BlockEntry
303 if (IndexLevel != PageLevel) {
304 // Retrieve the attributes from the block entry
305 Attributes = *BlockEntry & TT_ATTRIBUTES_MASK;
306
307 // Convert the block entry attributes into Table descriptor attributes
308 TableAttributes = TT_TABLE_AP_NO_PERMISSION;
309 if (Attributes & TT_PXN_MASK) {
310 TableAttributes = TT_TABLE_PXN;
311 }
312 // XN maps to UXN in the EL1&0 translation regime
313 if (Attributes & TT_XN_MASK) {
314 TableAttributes = TT_TABLE_XN;
315 }
316 if (Attributes & TT_NS) {
317 TableAttributes = TT_TABLE_NS;
318 }
319
320 // Get the address corresponding at this entry
321 BlockEntryAddress = RegionStart;
322 BlockEntryAddress = BlockEntryAddress >> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
323 // Shift back to right to set zero before the effective address
324 BlockEntryAddress = BlockEntryAddress << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
325
326 // Set the correct entry type for the next page level
327 if ((IndexLevel + 1) == 3) {
328 Attributes |= TT_TYPE_BLOCK_ENTRY_LEVEL3;
329 } else {
330 Attributes |= TT_TYPE_BLOCK_ENTRY;
331 }
332
333 // Create a new translation table
334 TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);
335 if (TranslationTable == NULL) {
336 return NULL;
337 }
338
339 // Populate the newly created lower level table
340 SubTableBlockEntry = TranslationTable;
341 for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
342 *SubTableBlockEntry = Attributes | (BlockEntryAddress + (Index << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel + 1)));
343 SubTableBlockEntry++;
344 }
345
346 // Fill the BlockEntry with the new TranslationTable
347 ReplaceLiveEntry (BlockEntry,
348 ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY);
349 }
350 } else {
351 if (IndexLevel != PageLevel) {
352 //
353 // Case when we have an Invalid Entry and we are at a page level above of the one targetted.
354 //
355
356 // Create a new translation table
357 TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);
358 if (TranslationTable == NULL) {
359 return NULL;
360 }
361
362 ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64));
363
364 // Fill the new BlockEntry with the TranslationTable
365 *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;
366 }
367 }
368 }
369
370 // Expose the found PageLevel to the caller
371 *TableLevel = PageLevel;
372
373 // Now, we have the Table Level we can get the Block Size associated to this table
374 *BlockEntrySize = TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel);
375
376 // The last block of the root table depends on the number of entry in this table,
377 // otherwise it is always the (TT_ENTRY_COUNT - 1)th entry in the table.
378 *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable,
379 (PageLevel == RootTableLevel) ? RootTableEntryCount : TT_ENTRY_COUNT);
380
381 return BlockEntry;
382 }
383
384 STATIC
385 RETURN_STATUS
386 UpdateRegionMapping (
387 IN UINT64 *RootTable,
388 IN UINT64 RegionStart,
389 IN UINT64 RegionLength,
390 IN UINT64 Attributes,
391 IN UINT64 BlockEntryMask
392 )
393 {
394 UINT32 Type;
395 UINT64 *BlockEntry;
396 UINT64 *LastBlockEntry;
397 UINT64 BlockEntrySize;
398 UINTN TableLevel;
399
400 // Ensure the Length is aligned on 4KB boundary
401 if ((RegionLength == 0) || ((RegionLength & (SIZE_4KB - 1)) != 0)) {
402 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
403 return RETURN_INVALID_PARAMETER;
404 }
405
406 do {
407 // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor
408 // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
409 BlockEntrySize = RegionLength;
410 BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);
411 if (BlockEntry == NULL) {
412 // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables
413 return RETURN_OUT_OF_RESOURCES;
414 }
415
416 if (TableLevel != 3) {
417 Type = TT_TYPE_BLOCK_ENTRY;
418 } else {
419 Type = TT_TYPE_BLOCK_ENTRY_LEVEL3;
420 }
421
422 do {
423 // Fill the Block Entry with attribute and output block address
424 *BlockEntry &= BlockEntryMask;
425 *BlockEntry |= (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type;
426
427 // Go to the next BlockEntry
428 RegionStart += BlockEntrySize;
429 RegionLength -= BlockEntrySize;
430 BlockEntry++;
431
432 // Break the inner loop when next block is a table
433 // Rerun GetBlockEntryListFromAddress to avoid page table memory leak
434 if (TableLevel != 3 &&
435 (*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
436 break;
437 }
438 } while ((RegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry));
439 } while (RegionLength != 0);
440
441 return RETURN_SUCCESS;
442 }
443
444 STATIC
445 RETURN_STATUS
446 FillTranslationTable (
447 IN UINT64 *RootTable,
448 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
449 )
450 {
451 return UpdateRegionMapping (
452 RootTable,
453 MemoryRegion->VirtualBase,
454 MemoryRegion->Length,
455 ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF,
456 0
457 );
458 }
459
460 RETURN_STATUS
461 SetMemoryAttributes (
462 IN EFI_PHYSICAL_ADDRESS BaseAddress,
463 IN UINT64 Length,
464 IN UINT64 Attributes,
465 IN EFI_PHYSICAL_ADDRESS VirtualMask
466 )
467 {
468 RETURN_STATUS Status;
469 ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion;
470 UINT64 *TranslationTable;
471
472 MemoryRegion.PhysicalBase = BaseAddress;
473 MemoryRegion.VirtualBase = BaseAddress;
474 MemoryRegion.Length = Length;
475 MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes);
476
477 TranslationTable = ArmGetTTBR0BaseAddress ();
478
479 Status = FillTranslationTable (TranslationTable, &MemoryRegion);
480 if (RETURN_ERROR (Status)) {
481 return Status;
482 }
483
484 // Invalidate all TLB entries so changes are synced
485 ArmInvalidateTlb ();
486
487 return RETURN_SUCCESS;
488 }
489
490 STATIC
491 RETURN_STATUS
492 SetMemoryRegionAttribute (
493 IN EFI_PHYSICAL_ADDRESS BaseAddress,
494 IN UINT64 Length,
495 IN UINT64 Attributes,
496 IN UINT64 BlockEntryMask
497 )
498 {
499 RETURN_STATUS Status;
500 UINT64 *RootTable;
501
502 RootTable = ArmGetTTBR0BaseAddress ();
503
504 Status = UpdateRegionMapping (RootTable, BaseAddress, Length, Attributes, BlockEntryMask);
505 if (RETURN_ERROR (Status)) {
506 return Status;
507 }
508
509 // Invalidate all TLB entries so changes are synced
510 ArmInvalidateTlb ();
511
512 return RETURN_SUCCESS;
513 }
514
515 RETURN_STATUS
516 ArmSetMemoryRegionNoExec (
517 IN EFI_PHYSICAL_ADDRESS BaseAddress,
518 IN UINT64 Length
519 )
520 {
521 UINT64 Val;
522
523 if (ArmReadCurrentEL () == AARCH64_EL1) {
524 Val = TT_PXN_MASK | TT_UXN_MASK;
525 } else {
526 Val = TT_XN_MASK;
527 }
528
529 return SetMemoryRegionAttribute (
530 BaseAddress,
531 Length,
532 Val,
533 ~TT_ADDRESS_MASK_BLOCK_ENTRY);
534 }
535
536 RETURN_STATUS
537 ArmClearMemoryRegionNoExec (
538 IN EFI_PHYSICAL_ADDRESS BaseAddress,
539 IN UINT64 Length
540 )
541 {
542 UINT64 Mask;
543
544 // XN maps to UXN in the EL1&0 translation regime
545 Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);
546
547 return SetMemoryRegionAttribute (
548 BaseAddress,
549 Length,
550 0,
551 Mask);
552 }
553
554 RETURN_STATUS
555 ArmSetMemoryRegionReadOnly (
556 IN EFI_PHYSICAL_ADDRESS BaseAddress,
557 IN UINT64 Length
558 )
559 {
560 return SetMemoryRegionAttribute (
561 BaseAddress,
562 Length,
563 TT_AP_RO_RO,
564 ~TT_ADDRESS_MASK_BLOCK_ENTRY);
565 }
566
567 RETURN_STATUS
568 ArmClearMemoryRegionReadOnly (
569 IN EFI_PHYSICAL_ADDRESS BaseAddress,
570 IN UINT64 Length
571 )
572 {
573 return SetMemoryRegionAttribute (
574 BaseAddress,
575 Length,
576 TT_AP_RW_RW,
577 ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));
578 }
579
580 RETURN_STATUS
581 EFIAPI
582 ArmConfigureMmu (
583 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
584 OUT VOID **TranslationTableBase OPTIONAL,
585 OUT UINTN *TranslationTableSize OPTIONAL
586 )
587 {
588 VOID* TranslationTable;
589 UINTN TranslationTablePageCount;
590 UINT32 TranslationTableAttribute;
591 ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry;
592 UINT64 MaxAddress;
593 UINT64 TopAddress;
594 UINTN T0SZ;
595 UINTN RootTableEntryCount;
596 UINT64 TCR;
597 RETURN_STATUS Status;
598
599 if(MemoryTable == NULL) {
600 ASSERT (MemoryTable != NULL);
601 return RETURN_INVALID_PARAMETER;
602 }
603
604 // Identify the highest address of the memory table
605 MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1;
606 MemoryTableEntry = MemoryTable;
607 while (MemoryTableEntry->Length != 0) {
608 TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1;
609 if (TopAddress > MaxAddress) {
610 MaxAddress = TopAddress;
611 }
612 MemoryTableEntry++;
613 }
614
615 // Lookup the Table Level to get the information
616 LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);
617
618 //
619 // Set TCR that allows us to retrieve T0SZ in the subsequent functions
620 //
621 // Ideally we will be running at EL2, but should support EL1 as well.
622 // UEFI should not run at EL3.
623 if (ArmReadCurrentEL () == AARCH64_EL2) {
624 //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
625 TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
626
627 // Set the Physical Address Size using MaxAddress
628 if (MaxAddress < SIZE_4GB) {
629 TCR |= TCR_PS_4GB;
630 } else if (MaxAddress < SIZE_64GB) {
631 TCR |= TCR_PS_64GB;
632 } else if (MaxAddress < SIZE_1TB) {
633 TCR |= TCR_PS_1TB;
634 } else if (MaxAddress < SIZE_4TB) {
635 TCR |= TCR_PS_4TB;
636 } else if (MaxAddress < SIZE_16TB) {
637 TCR |= TCR_PS_16TB;
638 } else if (MaxAddress < SIZE_256TB) {
639 TCR |= TCR_PS_256TB;
640 } else {
641 DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
642 ASSERT (0); // Bigger than 48-bit memory space are not supported
643 return RETURN_UNSUPPORTED;
644 }
645 } else if (ArmReadCurrentEL () == AARCH64_EL1) {
646 // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.
647 TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;
648
649 // Set the Physical Address Size using MaxAddress
650 if (MaxAddress < SIZE_4GB) {
651 TCR |= TCR_IPS_4GB;
652 } else if (MaxAddress < SIZE_64GB) {
653 TCR |= TCR_IPS_64GB;
654 } else if (MaxAddress < SIZE_1TB) {
655 TCR |= TCR_IPS_1TB;
656 } else if (MaxAddress < SIZE_4TB) {
657 TCR |= TCR_IPS_4TB;
658 } else if (MaxAddress < SIZE_16TB) {
659 TCR |= TCR_IPS_16TB;
660 } else if (MaxAddress < SIZE_256TB) {
661 TCR |= TCR_IPS_256TB;
662 } else {
663 DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
664 ASSERT (0); // Bigger than 48-bit memory space are not supported
665 return RETURN_UNSUPPORTED;
666 }
667 } else {
668 ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
669 return RETURN_UNSUPPORTED;
670 }
671
672 // Set TCR
673 ArmSetTCR (TCR);
674
675 // Allocate pages for translation table
676 TranslationTablePageCount = EFI_SIZE_TO_PAGES(RootTableEntryCount * sizeof(UINT64));
677 TranslationTable = (UINT64*)AllocateAlignedPages (TranslationTablePageCount, TT_ALIGNMENT_DESCRIPTION_TABLE);
678 if (TranslationTable == NULL) {
679 return RETURN_OUT_OF_RESOURCES;
680 }
681 // We set TTBR0 just after allocating the table to retrieve its location from the subsequent
682 // functions without needing to pass this value across the functions. The MMU is only enabled
683 // after the translation tables are populated.
684 ArmSetTTBR0 (TranslationTable);
685
686 if (TranslationTableBase != NULL) {
687 *TranslationTableBase = TranslationTable;
688 }
689
690 if (TranslationTableSize != NULL) {
691 *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);
692 }
693
694 ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
695
696 // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
697 ArmDisableMmu ();
698 ArmDisableDataCache ();
699 ArmDisableInstructionCache ();
700
701 // Make sure nothing sneaked into the cache
702 ArmCleanInvalidateDataCache ();
703 ArmInvalidateInstructionCache ();
704
705 TranslationTableAttribute = TT_ATTR_INDX_INVALID;
706 while (MemoryTable->Length != 0) {
707 // Find the memory attribute for the Translation Table
708 if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) &&
709 ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
710 TranslationTableAttribute = MemoryTable->Attributes;
711 }
712
713 Status = FillTranslationTable (TranslationTable, MemoryTable);
714 if (RETURN_ERROR (Status)) {
715 goto FREE_TRANSLATION_TABLE;
716 }
717 MemoryTable++;
718 }
719
720 // Translate the Memory Attributes into Translation Table Register Attributes
721 if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
722 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
723 TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE | TCR_RGN_INNER_NON_CACHEABLE;
724 } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
725 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
726 TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC | TCR_RGN_INNER_WRITE_BACK_ALLOC;
727 } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
728 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
729 TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH | TCR_RGN_INNER_WRITE_THROUGH;
730 } else {
731 // If we failed to find a mapping that contains the root translation table then it probably means the translation table
732 // is not mapped in the given memory map.
733 ASSERT (0);
734 Status = RETURN_UNSUPPORTED;
735 goto FREE_TRANSLATION_TABLE;
736 }
737
738 // Set again TCR after getting the Translation Table attributes
739 ArmSetTCR (TCR);
740
741 ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC
742 MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC
743 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT
744 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)); // mapped to EFI_MEMORY_WB
745
746 ArmDisableAlignmentCheck ();
747 ArmEnableInstructionCache ();
748 ArmEnableDataCache ();
749
750 ArmEnableMmu ();
751 return RETURN_SUCCESS;
752
753 FREE_TRANSLATION_TABLE:
754 FreePages (TranslationTable, TranslationTablePageCount);
755 return Status;
756 }
EFI Development Kit II mirror for PVE