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[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Mmu.c
1 /** @file
2 * File managing the MMU for ARMv8 architecture
3 *
4 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16 #include <Uefi.h>
17 #include <Chipset/AArch64.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/MemoryAllocationLib.h>
20 #include <Library/ArmLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/DebugLib.h>
23 #include "AArch64Lib.h"
24 #include "ArmLibPrivate.h"
25
26 // We use this index definition to define an invalid block entry
27 #define TT_ATTR_INDX_INVALID ((UINT32)~0)
28
29 STATIC
30 UINT64
31 ArmMemoryAttributeToPageAttribute (
32 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
33 )
34 {
35 switch (Attributes) {
36 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
37 return TT_ATTR_INDX_MEMORY_WRITE_BACK;
38 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
39 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
40 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
41 return TT_ATTR_INDX_DEVICE_MEMORY;
42 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
43 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
44 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
45 return TT_ATTR_INDX_MEMORY_WRITE_BACK;
46 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
47 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
48 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
49 return TT_ATTR_INDX_DEVICE_MEMORY;
50 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
51 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
52 default:
53 ASSERT(0);
54 return TT_ATTR_INDX_DEVICE_MEMORY;
55 }
56 }
57
58 UINT64
59 PageAttributeToGcdAttribute (
60 IN UINT64 PageAttributes
61 )
62 {
63 UINT64 GcdAttributes;
64
65 switch (PageAttributes & TT_ATTR_INDX_MASK) {
66 case TT_ATTR_INDX_DEVICE_MEMORY:
67 GcdAttributes = EFI_MEMORY_UC;
68 break;
69 case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
70 GcdAttributes = EFI_MEMORY_WC;
71 break;
72 case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
73 GcdAttributes = EFI_MEMORY_WT;
74 break;
75 case TT_ATTR_INDX_MEMORY_WRITE_BACK:
76 GcdAttributes = EFI_MEMORY_WB;
77 break;
78 default:
79 DEBUG ((EFI_D_ERROR, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes));
80 ASSERT (0);
81 // The Global Coherency Domain (GCD) value is defined as a bit set.
82 // Returning 0 means no attribute has been set.
83 GcdAttributes = 0;
84 }
85
86 // Determine protection attributes
87 if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
88 // Read only cases map to write-protect
89 GcdAttributes |= EFI_MEMORY_WP;
90 }
91
92 // Process eXecute Never attribute
93 if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0 ) {
94 GcdAttributes |= EFI_MEMORY_XP;
95 }
96
97 return GcdAttributes;
98 }
99
100 UINT64
101 GcdAttributeToPageAttribute (
102 IN UINT64 GcdAttributes
103 )
104 {
105 UINT64 PageAttributes;
106
107 switch (GcdAttributes & 0xFF) {
108 case EFI_MEMORY_UC:
109 PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
110 break;
111 case EFI_MEMORY_WC:
112 PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
113 break;
114 case EFI_MEMORY_WT:
115 PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
116 break;
117 case EFI_MEMORY_WB:
118 PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK;
119 break;
120 default:
121 DEBUG ((EFI_D_ERROR, "GcdAttributeToPageAttribute: 0x%X attributes is not supported.\n", GcdAttributes));
122 ASSERT (0);
123 // If no match has been found then we mark the memory as device memory.
124 // The only side effect of using device memory should be a slow down in the performance.
125 PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
126 }
127
128 // Determine protection attributes
129 if (GcdAttributes & EFI_MEMORY_WP) {
130 // Read only cases map to write-protect
131 PageAttributes |= TT_AP_RO_RO;
132 }
133
134 // Process eXecute Never attribute
135 if (GcdAttributes & EFI_MEMORY_XP) {
136 PageAttributes |= (TT_PXN_MASK | TT_UXN_MASK);
137 }
138
139 return PageAttributes;
140 }
141
142 ARM_MEMORY_REGION_ATTRIBUTES
143 GcdAttributeToArmAttribute (
144 IN UINT64 GcdAttributes
145 )
146 {
147 switch (GcdAttributes & 0xFF) {
148 case EFI_MEMORY_UC:
149 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
150 case EFI_MEMORY_WC:
151 return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
152 case EFI_MEMORY_WT:
153 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
154 case EFI_MEMORY_WB:
155 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
156 default:
157 DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes));
158 ASSERT (0);
159 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
160 }
161 }
162
163 // Describe the T0SZ values for each translation table level
164 typedef struct {
165 UINTN MinT0SZ;
166 UINTN MaxT0SZ;
167 UINTN LargestT0SZ; // Generally (MaxT0SZ == LargestT0SZ) but at the Level3 Table
168 // the MaxT0SZ is not at the boundary of the table
169 } T0SZ_DESCRIPTION_PER_LEVEL;
170
171 // Map table for the corresponding Level of Table
172 STATIC CONST T0SZ_DESCRIPTION_PER_LEVEL T0SZPerTableLevel[] = {
173 { 16, 24, 24 }, // Table Level 0
174 { 25, 33, 33 }, // Table Level 1
175 { 34, 39, 42 } // Table Level 2
176 };
177
178 VOID
179 GetRootTranslationTableInfo (
180 IN UINTN T0SZ,
181 OUT UINTN *TableLevel,
182 OUT UINTN *TableEntryCount
183 )
184 {
185 UINTN Index;
186
187 // Identify the level of the root table from the given T0SZ
188 for (Index = 0; Index < sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL); Index++) {
189 if (T0SZ <= T0SZPerTableLevel[Index].MaxT0SZ) {
190 break;
191 }
192 }
193
194 // If we have not found the corresponding maximum T0SZ then we use the last one
195 if (Index == sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL)) {
196 Index--;
197 }
198
199 // Get the level of the root table
200 if (TableLevel) {
201 *TableLevel = Index;
202 }
203
204 // The Size of the Table is 2^(T0SZ-LargestT0SZ)
205 if (TableEntryCount) {
206 *TableEntryCount = 1 << (T0SZPerTableLevel[Index].LargestT0SZ - T0SZ + 1);
207 }
208 }
209
210 STATIC
211 VOID
212 LookupAddresstoRootTable (
213 IN UINT64 MaxAddress,
214 OUT UINTN *T0SZ,
215 OUT UINTN *TableEntryCount
216 )
217 {
218 UINTN TopBit;
219
220 // Check the parameters are not NULL
221 ASSERT ((T0SZ != NULL) && (TableEntryCount != NULL));
222
223 // Look for the highest bit set in MaxAddress
224 for (TopBit = 63; TopBit != 0; TopBit--) {
225 if ((1ULL << TopBit) & MaxAddress) {
226 // MaxAddress top bit is found
227 TopBit = TopBit + 1;
228 break;
229 }
230 }
231 ASSERT (TopBit != 0);
232
233 // Calculate T0SZ from the top bit of the MaxAddress
234 *T0SZ = 64 - TopBit;
235
236 // Get the Table info from T0SZ
237 GetRootTranslationTableInfo (*T0SZ, NULL, TableEntryCount);
238 }
239
240 STATIC
241 UINT64*
242 GetBlockEntryListFromAddress (
243 IN UINT64 *RootTable,
244 IN UINT64 RegionStart,
245 OUT UINTN *TableLevel,
246 IN OUT UINT64 *BlockEntrySize,
247 OUT UINT64 **LastBlockEntry
248 )
249 {
250 UINTN RootTableLevel;
251 UINTN RootTableEntryCount;
252 UINT64 *TranslationTable;
253 UINT64 *BlockEntry;
254 UINT64 *SubTableBlockEntry;
255 UINT64 BlockEntryAddress;
256 UINTN BaseAddressAlignment;
257 UINTN PageLevel;
258 UINTN Index;
259 UINTN IndexLevel;
260 UINTN T0SZ;
261 UINT64 Attributes;
262 UINT64 TableAttributes;
263
264 // Initialize variable
265 BlockEntry = NULL;
266
267 // Ensure the parameters are valid
268 if (!(TableLevel && BlockEntrySize && LastBlockEntry)) {
269 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
270 return NULL;
271 }
272
273 // Ensure the Region is aligned on 4KB boundary
274 if ((RegionStart & (SIZE_4KB - 1)) != 0) {
275 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
276 return NULL;
277 }
278
279 // Ensure the required size is aligned on 4KB boundary and not 0
280 if ((*BlockEntrySize & (SIZE_4KB - 1)) != 0 || *BlockEntrySize == 0) {
281 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
282 return NULL;
283 }
284
285 T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
286 // Get the Table info from T0SZ
287 GetRootTranslationTableInfo (T0SZ, &RootTableLevel, &RootTableEntryCount);
288
289 // If the start address is 0x0 then we use the size of the region to identify the alignment
290 if (RegionStart == 0) {
291 // Identify the highest possible alignment for the Region Size
292 BaseAddressAlignment = LowBitSet64 (*BlockEntrySize);
293 } else {
294 // Identify the highest possible alignment for the Base Address
295 BaseAddressAlignment = LowBitSet64 (RegionStart);
296 }
297
298 // Identify the Page Level the RegionStart must belong to. Note that PageLevel
299 // should be at least 1 since block translations are not supported at level 0
300 PageLevel = MAX (3 - ((BaseAddressAlignment - 12) / 9), 1);
301
302 // If the required size is smaller than the current block size then we need to go to the page below.
303 // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment
304 // of the allocation size
305 while (*BlockEntrySize < TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel)) {
306 // It does not fit so we need to go a page level above
307 PageLevel++;
308 }
309
310 //
311 // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries
312 //
313
314 TranslationTable = RootTable;
315 for (IndexLevel = RootTableLevel; IndexLevel <= PageLevel; IndexLevel++) {
316 BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel, RegionStart);
317
318 if ((IndexLevel != 3) && ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {
319 // Go to the next table
320 TranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
321
322 // If we are at the last level then update the last level to next level
323 if (IndexLevel == PageLevel) {
324 // Enter the next level
325 PageLevel++;
326 }
327 } else if ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) {
328 // If we are not at the last level then we need to split this BlockEntry
329 if (IndexLevel != PageLevel) {
330 // Retrieve the attributes from the block entry
331 Attributes = *BlockEntry & TT_ATTRIBUTES_MASK;
332
333 // Convert the block entry attributes into Table descriptor attributes
334 TableAttributes = TT_TABLE_AP_NO_PERMISSION;
335 if (Attributes & TT_PXN_MASK) {
336 TableAttributes = TT_TABLE_PXN;
337 }
338 // XN maps to UXN in the EL1&0 translation regime
339 if (Attributes & TT_XN_MASK) {
340 TableAttributes = TT_TABLE_XN;
341 }
342 if (Attributes & TT_NS) {
343 TableAttributes = TT_TABLE_NS;
344 }
345
346 // Get the address corresponding at this entry
347 BlockEntryAddress = RegionStart;
348 BlockEntryAddress = BlockEntryAddress >> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
349 // Shift back to right to set zero before the effective address
350 BlockEntryAddress = BlockEntryAddress << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
351
352 // Set the correct entry type for the next page level
353 if ((IndexLevel + 1) == 3) {
354 Attributes |= TT_TYPE_BLOCK_ENTRY_LEVEL3;
355 } else {
356 Attributes |= TT_TYPE_BLOCK_ENTRY;
357 }
358
359 // Create a new translation table
360 TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);
361 if (TranslationTable == NULL) {
362 return NULL;
363 }
364
365 // Populate the newly created lower level table
366 SubTableBlockEntry = TranslationTable;
367 for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
368 *SubTableBlockEntry = Attributes | (BlockEntryAddress + (Index << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel + 1)));
369 SubTableBlockEntry++;
370 }
371
372 // Fill the BlockEntry with the new TranslationTable
373 *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY;
374 }
375 } else {
376 if (IndexLevel != PageLevel) {
377 //
378 // Case when we have an Invalid Entry and we are at a page level above of the one targetted.
379 //
380
381 // Create a new translation table
382 TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);
383 if (TranslationTable == NULL) {
384 return NULL;
385 }
386
387 ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64));
388
389 // Fill the new BlockEntry with the TranslationTable
390 *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;
391 }
392 }
393 }
394
395 // Expose the found PageLevel to the caller
396 *TableLevel = PageLevel;
397
398 // Now, we have the Table Level we can get the Block Size associated to this table
399 *BlockEntrySize = TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel);
400
401 // The last block of the root table depends on the number of entry in this table,
402 // otherwise it is always the (TT_ENTRY_COUNT - 1)th entry in the table.
403 *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable,
404 (PageLevel == RootTableLevel) ? RootTableEntryCount : TT_ENTRY_COUNT);
405
406 return BlockEntry;
407 }
408
409 STATIC
410 RETURN_STATUS
411 UpdateRegionMapping (
412 IN UINT64 *RootTable,
413 IN UINT64 RegionStart,
414 IN UINT64 RegionLength,
415 IN UINT64 Attributes,
416 IN UINT64 BlockEntryMask
417 )
418 {
419 UINT32 Type;
420 UINT64 *BlockEntry;
421 UINT64 *LastBlockEntry;
422 UINT64 BlockEntrySize;
423 UINTN TableLevel;
424
425 // Ensure the Length is aligned on 4KB boundary
426 if ((RegionLength == 0) || ((RegionLength & (SIZE_4KB - 1)) != 0)) {
427 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
428 return RETURN_INVALID_PARAMETER;
429 }
430
431 do {
432 // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor
433 // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
434 BlockEntrySize = RegionLength;
435 BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);
436 if (BlockEntry == NULL) {
437 // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables
438 return RETURN_OUT_OF_RESOURCES;
439 }
440
441 if (TableLevel != 3) {
442 Type = TT_TYPE_BLOCK_ENTRY;
443 } else {
444 Type = TT_TYPE_BLOCK_ENTRY_LEVEL3;
445 }
446
447 do {
448 // Fill the Block Entry with attribute and output block address
449 *BlockEntry &= BlockEntryMask;
450 *BlockEntry |= (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type;
451
452 // Go to the next BlockEntry
453 RegionStart += BlockEntrySize;
454 RegionLength -= BlockEntrySize;
455 BlockEntry++;
456
457 // Break the inner loop when next block is a table
458 // Rerun GetBlockEntryListFromAddress to avoid page table memory leak
459 if (TableLevel != 3 &&
460 (*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
461 break;
462 }
463 } while ((RegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry));
464 } while (RegionLength != 0);
465
466 return RETURN_SUCCESS;
467 }
468
469 STATIC
470 RETURN_STATUS
471 FillTranslationTable (
472 IN UINT64 *RootTable,
473 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
474 )
475 {
476 return UpdateRegionMapping (
477 RootTable,
478 MemoryRegion->VirtualBase,
479 MemoryRegion->Length,
480 ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF,
481 0
482 );
483 }
484
485 RETURN_STATUS
486 SetMemoryAttributes (
487 IN EFI_PHYSICAL_ADDRESS BaseAddress,
488 IN UINT64 Length,
489 IN UINT64 Attributes,
490 IN EFI_PHYSICAL_ADDRESS VirtualMask
491 )
492 {
493 RETURN_STATUS Status;
494 ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion;
495 UINT64 *TranslationTable;
496
497 MemoryRegion.PhysicalBase = BaseAddress;
498 MemoryRegion.VirtualBase = BaseAddress;
499 MemoryRegion.Length = Length;
500 MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes);
501
502 TranslationTable = ArmGetTTBR0BaseAddress ();
503
504 Status = FillTranslationTable (TranslationTable, &MemoryRegion);
505 if (RETURN_ERROR (Status)) {
506 return Status;
507 }
508
509 // Invalidate all TLB entries so changes are synced
510 ArmInvalidateTlb ();
511
512 return RETURN_SUCCESS;
513 }
514
515 RETURN_STATUS
516 EFIAPI
517 ArmConfigureMmu (
518 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
519 OUT VOID **TranslationTableBase OPTIONAL,
520 OUT UINTN *TranslationTableSize OPTIONAL
521 )
522 {
523 VOID* TranslationTable;
524 UINTN TranslationTablePageCount;
525 UINT32 TranslationTableAttribute;
526 ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry;
527 UINT64 MaxAddress;
528 UINT64 TopAddress;
529 UINTN T0SZ;
530 UINTN RootTableEntryCount;
531 UINT64 TCR;
532 RETURN_STATUS Status;
533
534 if(MemoryTable == NULL) {
535 ASSERT (MemoryTable != NULL);
536 return RETURN_INVALID_PARAMETER;
537 }
538
539 // Identify the highest address of the memory table
540 MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1;
541 MemoryTableEntry = MemoryTable;
542 while (MemoryTableEntry->Length != 0) {
543 TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1;
544 if (TopAddress > MaxAddress) {
545 MaxAddress = TopAddress;
546 }
547 MemoryTableEntry++;
548 }
549
550 // Lookup the Table Level to get the information
551 LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);
552
553 //
554 // Set TCR that allows us to retrieve T0SZ in the subsequent functions
555 //
556 // Ideally we will be running at EL2, but should support EL1 as well.
557 // UEFI should not run at EL3.
558 if (ArmReadCurrentEL () == AARCH64_EL2) {
559 //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
560 TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
561
562 // Set the Physical Address Size using MaxAddress
563 if (MaxAddress < SIZE_4GB) {
564 TCR |= TCR_PS_4GB;
565 } else if (MaxAddress < SIZE_64GB) {
566 TCR |= TCR_PS_64GB;
567 } else if (MaxAddress < SIZE_1TB) {
568 TCR |= TCR_PS_1TB;
569 } else if (MaxAddress < SIZE_4TB) {
570 TCR |= TCR_PS_4TB;
571 } else if (MaxAddress < SIZE_16TB) {
572 TCR |= TCR_PS_16TB;
573 } else if (MaxAddress < SIZE_256TB) {
574 TCR |= TCR_PS_256TB;
575 } else {
576 DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
577 ASSERT (0); // Bigger than 48-bit memory space are not supported
578 return RETURN_UNSUPPORTED;
579 }
580 } else if (ArmReadCurrentEL () == AARCH64_EL1) {
581 TCR = T0SZ | TCR_TG0_4KB;
582
583 // Set the Physical Address Size using MaxAddress
584 if (MaxAddress < SIZE_4GB) {
585 TCR |= TCR_IPS_4GB;
586 } else if (MaxAddress < SIZE_64GB) {
587 TCR |= TCR_IPS_64GB;
588 } else if (MaxAddress < SIZE_1TB) {
589 TCR |= TCR_IPS_1TB;
590 } else if (MaxAddress < SIZE_4TB) {
591 TCR |= TCR_IPS_4TB;
592 } else if (MaxAddress < SIZE_16TB) {
593 TCR |= TCR_IPS_16TB;
594 } else if (MaxAddress < SIZE_256TB) {
595 TCR |= TCR_IPS_256TB;
596 } else {
597 DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
598 ASSERT (0); // Bigger than 48-bit memory space are not supported
599 return RETURN_UNSUPPORTED;
600 }
601 } else {
602 ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
603 return RETURN_UNSUPPORTED;
604 }
605
606 // Set TCR
607 ArmSetTCR (TCR);
608
609 // Allocate pages for translation table
610 TranslationTablePageCount = EFI_SIZE_TO_PAGES(RootTableEntryCount * sizeof(UINT64));
611 TranslationTable = (UINT64*)AllocateAlignedPages (TranslationTablePageCount, TT_ALIGNMENT_DESCRIPTION_TABLE);
612 if (TranslationTable == NULL) {
613 return RETURN_OUT_OF_RESOURCES;
614 }
615 // We set TTBR0 just after allocating the table to retrieve its location from the subsequent
616 // functions without needing to pass this value across the functions. The MMU is only enabled
617 // after the translation tables are populated.
618 ArmSetTTBR0 (TranslationTable);
619
620 if (TranslationTableBase != NULL) {
621 *TranslationTableBase = TranslationTable;
622 }
623
624 if (TranslationTableSize != NULL) {
625 *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);
626 }
627
628 ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
629
630 // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
631 ArmDisableMmu ();
632 ArmDisableDataCache ();
633 ArmDisableInstructionCache ();
634
635 // Make sure nothing sneaked into the cache
636 ArmCleanInvalidateDataCache ();
637 ArmInvalidateInstructionCache ();
638
639 TranslationTableAttribute = TT_ATTR_INDX_INVALID;
640 while (MemoryTable->Length != 0) {
641 // Find the memory attribute for the Translation Table
642 if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) &&
643 ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
644 TranslationTableAttribute = MemoryTable->Attributes;
645 }
646
647 Status = FillTranslationTable (TranslationTable, MemoryTable);
648 if (RETURN_ERROR (Status)) {
649 goto FREE_TRANSLATION_TABLE;
650 }
651 MemoryTable++;
652 }
653
654 // Translate the Memory Attributes into Translation Table Register Attributes
655 if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
656 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
657 TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE | TCR_RGN_INNER_NON_CACHEABLE;
658 } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
659 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
660 TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC | TCR_RGN_INNER_WRITE_BACK_ALLOC;
661 } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
662 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
663 TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH | TCR_RGN_INNER_WRITE_THROUGH;
664 } else {
665 // If we failed to find a mapping that contains the root translation table then it probably means the translation table
666 // is not mapped in the given memory map.
667 ASSERT (0);
668 Status = RETURN_UNSUPPORTED;
669 goto FREE_TRANSLATION_TABLE;
670 }
671
672 // Set again TCR after getting the Translation Table attributes
673 ArmSetTCR (TCR);
674
675 ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC
676 MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC
677 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT
678 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)); // mapped to EFI_MEMORY_WB
679
680 ArmDisableAlignmentCheck ();
681 ArmEnableInstructionCache ();
682 ArmEnableDataCache ();
683
684 ArmEnableMmu ();
685 return RETURN_SUCCESS;
686
687 FREE_TRANSLATION_TABLE:
688 FreePages (TranslationTable, TranslationTablePageCount);
689 return Status;
690 }
EFI Development Kit II mirror for PVE