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[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Mmu.c
1 /** @file
2 * File managing the MMU for ARMv8 architecture
3 *
4 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16 #include <Uefi.h>
17 #include <Chipset/AArch64.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/MemoryAllocationLib.h>
20 #include <Library/ArmLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/DebugLib.h>
23 #include "AArch64Lib.h"
24 #include "ArmLibPrivate.h"
25
26 // We use this index definition to define an invalid block entry
27 #define TT_ATTR_INDX_INVALID ((UINT32)~0)
28
29 STATIC
30 UINT64
31 ArmMemoryAttributeToPageAttribute (
32 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
33 )
34 {
35 switch (Attributes) {
36 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
37 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
38 return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
39
40 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
41 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
42 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
43
44 // Uncached and device mappings are treated as outer shareable by default,
45 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
46 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
47 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
48
49 default:
50 ASSERT(0);
51 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
52 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
53 return TT_ATTR_INDX_DEVICE_MEMORY;
54 }
55 }
56
57 UINT64
58 PageAttributeToGcdAttribute (
59 IN UINT64 PageAttributes
60 )
61 {
62 UINT64 GcdAttributes;
63
64 switch (PageAttributes & TT_ATTR_INDX_MASK) {
65 case TT_ATTR_INDX_DEVICE_MEMORY:
66 GcdAttributes = EFI_MEMORY_UC;
67 break;
68 case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
69 GcdAttributes = EFI_MEMORY_WC;
70 break;
71 case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
72 GcdAttributes = EFI_MEMORY_WT;
73 break;
74 case TT_ATTR_INDX_MEMORY_WRITE_BACK:
75 GcdAttributes = EFI_MEMORY_WB;
76 break;
77 default:
78 DEBUG ((EFI_D_ERROR, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes));
79 ASSERT (0);
80 // The Global Coherency Domain (GCD) value is defined as a bit set.
81 // Returning 0 means no attribute has been set.
82 GcdAttributes = 0;
83 }
84
85 // Determine protection attributes
86 if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
87 // Read only cases map to write-protect
88 GcdAttributes |= EFI_MEMORY_WP;
89 }
90
91 // Process eXecute Never attribute
92 if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0 ) {
93 GcdAttributes |= EFI_MEMORY_XP;
94 }
95
96 return GcdAttributes;
97 }
98
99 UINT64
100 GcdAttributeToPageAttribute (
101 IN UINT64 GcdAttributes
102 )
103 {
104 UINT64 PageAttributes;
105
106 switch (GcdAttributes & 0xFF) {
107 case EFI_MEMORY_UC:
108 PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
109 break;
110 case EFI_MEMORY_WC:
111 PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
112 break;
113 case EFI_MEMORY_WT:
114 PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
115 break;
116 case EFI_MEMORY_WB:
117 PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK;
118 break;
119 default:
120 DEBUG ((EFI_D_ERROR, "GcdAttributeToPageAttribute: 0x%X attributes is not supported.\n", GcdAttributes));
121 ASSERT (0);
122 // If no match has been found then we mark the memory as device memory.
123 // The only side effect of using device memory should be a slow down in the performance.
124 PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
125 }
126
127 // Determine protection attributes
128 if (GcdAttributes & EFI_MEMORY_WP) {
129 // Read only cases map to write-protect
130 PageAttributes |= TT_AP_RO_RO;
131 }
132
133 // Process eXecute Never attribute
134 if (GcdAttributes & EFI_MEMORY_XP) {
135 PageAttributes |= (TT_PXN_MASK | TT_UXN_MASK);
136 }
137
138 return PageAttributes;
139 }
140
141 ARM_MEMORY_REGION_ATTRIBUTES
142 GcdAttributeToArmAttribute (
143 IN UINT64 GcdAttributes
144 )
145 {
146 switch (GcdAttributes & 0xFF) {
147 case EFI_MEMORY_UC:
148 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
149 case EFI_MEMORY_WC:
150 return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
151 case EFI_MEMORY_WT:
152 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
153 case EFI_MEMORY_WB:
154 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
155 default:
156 DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes));
157 ASSERT (0);
158 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
159 }
160 }
161
162 // Describe the T0SZ values for each translation table level
163 typedef struct {
164 UINTN MinT0SZ;
165 UINTN MaxT0SZ;
166 UINTN LargestT0SZ; // Generally (MaxT0SZ == LargestT0SZ) but at the Level3 Table
167 // the MaxT0SZ is not at the boundary of the table
168 } T0SZ_DESCRIPTION_PER_LEVEL;
169
170 // Map table for the corresponding Level of Table
171 STATIC CONST T0SZ_DESCRIPTION_PER_LEVEL T0SZPerTableLevel[] = {
172 { 16, 24, 24 }, // Table Level 0
173 { 25, 33, 33 }, // Table Level 1
174 { 34, 39, 42 } // Table Level 2
175 };
176
177 VOID
178 GetRootTranslationTableInfo (
179 IN UINTN T0SZ,
180 OUT UINTN *TableLevel,
181 OUT UINTN *TableEntryCount
182 )
183 {
184 UINTN Index;
185
186 // Identify the level of the root table from the given T0SZ
187 for (Index = 0; Index < sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL); Index++) {
188 if (T0SZ <= T0SZPerTableLevel[Index].MaxT0SZ) {
189 break;
190 }
191 }
192
193 // If we have not found the corresponding maximum T0SZ then we use the last one
194 if (Index == sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL)) {
195 Index--;
196 }
197
198 // Get the level of the root table
199 if (TableLevel) {
200 *TableLevel = Index;
201 }
202
203 // The Size of the Table is 2^(T0SZ-LargestT0SZ)
204 if (TableEntryCount) {
205 *TableEntryCount = 1 << (T0SZPerTableLevel[Index].LargestT0SZ - T0SZ + 1);
206 }
207 }
208
209 STATIC
210 VOID
211 LookupAddresstoRootTable (
212 IN UINT64 MaxAddress,
213 OUT UINTN *T0SZ,
214 OUT UINTN *TableEntryCount
215 )
216 {
217 UINTN TopBit;
218
219 // Check the parameters are not NULL
220 ASSERT ((T0SZ != NULL) && (TableEntryCount != NULL));
221
222 // Look for the highest bit set in MaxAddress
223 for (TopBit = 63; TopBit != 0; TopBit--) {
224 if ((1ULL << TopBit) & MaxAddress) {
225 // MaxAddress top bit is found
226 TopBit = TopBit + 1;
227 break;
228 }
229 }
230 ASSERT (TopBit != 0);
231
232 // Calculate T0SZ from the top bit of the MaxAddress
233 *T0SZ = 64 - TopBit;
234
235 // Get the Table info from T0SZ
236 GetRootTranslationTableInfo (*T0SZ, NULL, TableEntryCount);
237 }
238
239 STATIC
240 UINT64*
241 GetBlockEntryListFromAddress (
242 IN UINT64 *RootTable,
243 IN UINT64 RegionStart,
244 OUT UINTN *TableLevel,
245 IN OUT UINT64 *BlockEntrySize,
246 OUT UINT64 **LastBlockEntry
247 )
248 {
249 UINTN RootTableLevel;
250 UINTN RootTableEntryCount;
251 UINT64 *TranslationTable;
252 UINT64 *BlockEntry;
253 UINT64 *SubTableBlockEntry;
254 UINT64 BlockEntryAddress;
255 UINTN BaseAddressAlignment;
256 UINTN PageLevel;
257 UINTN Index;
258 UINTN IndexLevel;
259 UINTN T0SZ;
260 UINT64 Attributes;
261 UINT64 TableAttributes;
262
263 // Initialize variable
264 BlockEntry = NULL;
265
266 // Ensure the parameters are valid
267 if (!(TableLevel && BlockEntrySize && LastBlockEntry)) {
268 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
269 return NULL;
270 }
271
272 // Ensure the Region is aligned on 4KB boundary
273 if ((RegionStart & (SIZE_4KB - 1)) != 0) {
274 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
275 return NULL;
276 }
277
278 // Ensure the required size is aligned on 4KB boundary and not 0
279 if ((*BlockEntrySize & (SIZE_4KB - 1)) != 0 || *BlockEntrySize == 0) {
280 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
281 return NULL;
282 }
283
284 T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
285 // Get the Table info from T0SZ
286 GetRootTranslationTableInfo (T0SZ, &RootTableLevel, &RootTableEntryCount);
287
288 // If the start address is 0x0 then we use the size of the region to identify the alignment
289 if (RegionStart == 0) {
290 // Identify the highest possible alignment for the Region Size
291 BaseAddressAlignment = LowBitSet64 (*BlockEntrySize);
292 } else {
293 // Identify the highest possible alignment for the Base Address
294 BaseAddressAlignment = LowBitSet64 (RegionStart);
295 }
296
297 // Identify the Page Level the RegionStart must belong to. Note that PageLevel
298 // should be at least 1 since block translations are not supported at level 0
299 PageLevel = MAX (3 - ((BaseAddressAlignment - 12) / 9), 1);
300
301 // If the required size is smaller than the current block size then we need to go to the page below.
302 // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment
303 // of the allocation size
304 while (*BlockEntrySize < TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel)) {
305 // It does not fit so we need to go a page level above
306 PageLevel++;
307 }
308
309 //
310 // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries
311 //
312
313 TranslationTable = RootTable;
314 for (IndexLevel = RootTableLevel; IndexLevel <= PageLevel; IndexLevel++) {
315 BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel, RegionStart);
316
317 if ((IndexLevel != 3) && ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {
318 // Go to the next table
319 TranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
320
321 // If we are at the last level then update the last level to next level
322 if (IndexLevel == PageLevel) {
323 // Enter the next level
324 PageLevel++;
325 }
326 } else if ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) {
327 // If we are not at the last level then we need to split this BlockEntry
328 if (IndexLevel != PageLevel) {
329 // Retrieve the attributes from the block entry
330 Attributes = *BlockEntry & TT_ATTRIBUTES_MASK;
331
332 // Convert the block entry attributes into Table descriptor attributes
333 TableAttributes = TT_TABLE_AP_NO_PERMISSION;
334 if (Attributes & TT_PXN_MASK) {
335 TableAttributes = TT_TABLE_PXN;
336 }
337 // XN maps to UXN in the EL1&0 translation regime
338 if (Attributes & TT_XN_MASK) {
339 TableAttributes = TT_TABLE_XN;
340 }
341 if (Attributes & TT_NS) {
342 TableAttributes = TT_TABLE_NS;
343 }
344
345 // Get the address corresponding at this entry
346 BlockEntryAddress = RegionStart;
347 BlockEntryAddress = BlockEntryAddress >> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
348 // Shift back to right to set zero before the effective address
349 BlockEntryAddress = BlockEntryAddress << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
350
351 // Set the correct entry type for the next page level
352 if ((IndexLevel + 1) == 3) {
353 Attributes |= TT_TYPE_BLOCK_ENTRY_LEVEL3;
354 } else {
355 Attributes |= TT_TYPE_BLOCK_ENTRY;
356 }
357
358 // Create a new translation table
359 TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);
360 if (TranslationTable == NULL) {
361 return NULL;
362 }
363
364 // Populate the newly created lower level table
365 SubTableBlockEntry = TranslationTable;
366 for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
367 *SubTableBlockEntry = Attributes | (BlockEntryAddress + (Index << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel + 1)));
368 SubTableBlockEntry++;
369 }
370
371 // Fill the BlockEntry with the new TranslationTable
372 *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY;
373 }
374 } else {
375 if (IndexLevel != PageLevel) {
376 //
377 // Case when we have an Invalid Entry and we are at a page level above of the one targetted.
378 //
379
380 // Create a new translation table
381 TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);
382 if (TranslationTable == NULL) {
383 return NULL;
384 }
385
386 ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64));
387
388 // Fill the new BlockEntry with the TranslationTable
389 *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;
390 }
391 }
392 }
393
394 // Expose the found PageLevel to the caller
395 *TableLevel = PageLevel;
396
397 // Now, we have the Table Level we can get the Block Size associated to this table
398 *BlockEntrySize = TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel);
399
400 // The last block of the root table depends on the number of entry in this table,
401 // otherwise it is always the (TT_ENTRY_COUNT - 1)th entry in the table.
402 *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable,
403 (PageLevel == RootTableLevel) ? RootTableEntryCount : TT_ENTRY_COUNT);
404
405 return BlockEntry;
406 }
407
408 STATIC
409 RETURN_STATUS
410 UpdateRegionMapping (
411 IN UINT64 *RootTable,
412 IN UINT64 RegionStart,
413 IN UINT64 RegionLength,
414 IN UINT64 Attributes,
415 IN UINT64 BlockEntryMask
416 )
417 {
418 UINT32 Type;
419 UINT64 *BlockEntry;
420 UINT64 *LastBlockEntry;
421 UINT64 BlockEntrySize;
422 UINTN TableLevel;
423
424 // Ensure the Length is aligned on 4KB boundary
425 if ((RegionLength == 0) || ((RegionLength & (SIZE_4KB - 1)) != 0)) {
426 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
427 return RETURN_INVALID_PARAMETER;
428 }
429
430 do {
431 // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor
432 // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
433 BlockEntrySize = RegionLength;
434 BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);
435 if (BlockEntry == NULL) {
436 // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables
437 return RETURN_OUT_OF_RESOURCES;
438 }
439
440 if (TableLevel != 3) {
441 Type = TT_TYPE_BLOCK_ENTRY;
442 } else {
443 Type = TT_TYPE_BLOCK_ENTRY_LEVEL3;
444 }
445
446 do {
447 // Fill the Block Entry with attribute and output block address
448 *BlockEntry &= BlockEntryMask;
449 *BlockEntry |= (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type;
450
451 // Go to the next BlockEntry
452 RegionStart += BlockEntrySize;
453 RegionLength -= BlockEntrySize;
454 BlockEntry++;
455
456 // Break the inner loop when next block is a table
457 // Rerun GetBlockEntryListFromAddress to avoid page table memory leak
458 if (TableLevel != 3 &&
459 (*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
460 break;
461 }
462 } while ((RegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry));
463 } while (RegionLength != 0);
464
465 return RETURN_SUCCESS;
466 }
467
468 STATIC
469 RETURN_STATUS
470 FillTranslationTable (
471 IN UINT64 *RootTable,
472 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
473 )
474 {
475 return UpdateRegionMapping (
476 RootTable,
477 MemoryRegion->VirtualBase,
478 MemoryRegion->Length,
479 ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF,
480 0
481 );
482 }
483
484 RETURN_STATUS
485 SetMemoryAttributes (
486 IN EFI_PHYSICAL_ADDRESS BaseAddress,
487 IN UINT64 Length,
488 IN UINT64 Attributes,
489 IN EFI_PHYSICAL_ADDRESS VirtualMask
490 )
491 {
492 RETURN_STATUS Status;
493 ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion;
494 UINT64 *TranslationTable;
495
496 MemoryRegion.PhysicalBase = BaseAddress;
497 MemoryRegion.VirtualBase = BaseAddress;
498 MemoryRegion.Length = Length;
499 MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes);
500
501 TranslationTable = ArmGetTTBR0BaseAddress ();
502
503 Status = FillTranslationTable (TranslationTable, &MemoryRegion);
504 if (RETURN_ERROR (Status)) {
505 return Status;
506 }
507
508 // Invalidate all TLB entries so changes are synced
509 ArmInvalidateTlb ();
510
511 return RETURN_SUCCESS;
512 }
513
514 STATIC
515 RETURN_STATUS
516 SetMemoryRegionAttribute (
517 IN EFI_PHYSICAL_ADDRESS BaseAddress,
518 IN UINT64 Length,
519 IN UINT64 Attributes,
520 IN UINT64 BlockEntryMask
521 )
522 {
523 RETURN_STATUS Status;
524 UINT64 *RootTable;
525
526 RootTable = ArmGetTTBR0BaseAddress ();
527
528 Status = UpdateRegionMapping (RootTable, BaseAddress, Length, Attributes, BlockEntryMask);
529 if (RETURN_ERROR (Status)) {
530 return Status;
531 }
532
533 // Invalidate all TLB entries so changes are synced
534 ArmInvalidateTlb ();
535
536 return RETURN_SUCCESS;
537 }
538
539 RETURN_STATUS
540 ArmSetMemoryRegionNoExec (
541 IN EFI_PHYSICAL_ADDRESS BaseAddress,
542 IN UINT64 Length
543 )
544 {
545 UINT64 Val;
546
547 if (ArmReadCurrentEL () == AARCH64_EL1) {
548 Val = TT_PXN_MASK | TT_UXN_MASK;
549 } else {
550 Val = TT_XN_MASK;
551 }
552
553 return SetMemoryRegionAttribute (
554 BaseAddress,
555 Length,
556 Val,
557 ~TT_ADDRESS_MASK_BLOCK_ENTRY);
558 }
559
560 RETURN_STATUS
561 ArmClearMemoryRegionNoExec (
562 IN EFI_PHYSICAL_ADDRESS BaseAddress,
563 IN UINT64 Length
564 )
565 {
566 UINT64 Mask;
567
568 // XN maps to UXN in the EL1&0 translation regime
569 Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);
570
571 return SetMemoryRegionAttribute (
572 BaseAddress,
573 Length,
574 0,
575 Mask);
576 }
577
578 RETURN_STATUS
579 ArmSetMemoryRegionReadOnly (
580 IN EFI_PHYSICAL_ADDRESS BaseAddress,
581 IN UINT64 Length
582 )
583 {
584 return SetMemoryRegionAttribute (
585 BaseAddress,
586 Length,
587 TT_AP_RO_RO,
588 ~TT_ADDRESS_MASK_BLOCK_ENTRY);
589 }
590
591 RETURN_STATUS
592 ArmClearMemoryRegionReadOnly (
593 IN EFI_PHYSICAL_ADDRESS BaseAddress,
594 IN UINT64 Length
595 )
596 {
597 return SetMemoryRegionAttribute (
598 BaseAddress,
599 Length,
600 TT_AP_NO_RO,
601 ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));
602 }
603
604 RETURN_STATUS
605 EFIAPI
606 ArmConfigureMmu (
607 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
608 OUT VOID **TranslationTableBase OPTIONAL,
609 OUT UINTN *TranslationTableSize OPTIONAL
610 )
611 {
612 VOID* TranslationTable;
613 UINTN TranslationTablePageCount;
614 UINT32 TranslationTableAttribute;
615 ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry;
616 UINT64 MaxAddress;
617 UINT64 TopAddress;
618 UINTN T0SZ;
619 UINTN RootTableEntryCount;
620 UINT64 TCR;
621 RETURN_STATUS Status;
622
623 if(MemoryTable == NULL) {
624 ASSERT (MemoryTable != NULL);
625 return RETURN_INVALID_PARAMETER;
626 }
627
628 // Identify the highest address of the memory table
629 MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1;
630 MemoryTableEntry = MemoryTable;
631 while (MemoryTableEntry->Length != 0) {
632 TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1;
633 if (TopAddress > MaxAddress) {
634 MaxAddress = TopAddress;
635 }
636 MemoryTableEntry++;
637 }
638
639 // Lookup the Table Level to get the information
640 LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);
641
642 //
643 // Set TCR that allows us to retrieve T0SZ in the subsequent functions
644 //
645 // Ideally we will be running at EL2, but should support EL1 as well.
646 // UEFI should not run at EL3.
647 if (ArmReadCurrentEL () == AARCH64_EL2) {
648 //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
649 TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
650
651 // Set the Physical Address Size using MaxAddress
652 if (MaxAddress < SIZE_4GB) {
653 TCR |= TCR_PS_4GB;
654 } else if (MaxAddress < SIZE_64GB) {
655 TCR |= TCR_PS_64GB;
656 } else if (MaxAddress < SIZE_1TB) {
657 TCR |= TCR_PS_1TB;
658 } else if (MaxAddress < SIZE_4TB) {
659 TCR |= TCR_PS_4TB;
660 } else if (MaxAddress < SIZE_16TB) {
661 TCR |= TCR_PS_16TB;
662 } else if (MaxAddress < SIZE_256TB) {
663 TCR |= TCR_PS_256TB;
664 } else {
665 DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
666 ASSERT (0); // Bigger than 48-bit memory space are not supported
667 return RETURN_UNSUPPORTED;
668 }
669 } else if (ArmReadCurrentEL () == AARCH64_EL1) {
670 TCR = T0SZ | TCR_TG0_4KB;
671
672 // Set the Physical Address Size using MaxAddress
673 if (MaxAddress < SIZE_4GB) {
674 TCR |= TCR_IPS_4GB;
675 } else if (MaxAddress < SIZE_64GB) {
676 TCR |= TCR_IPS_64GB;
677 } else if (MaxAddress < SIZE_1TB) {
678 TCR |= TCR_IPS_1TB;
679 } else if (MaxAddress < SIZE_4TB) {
680 TCR |= TCR_IPS_4TB;
681 } else if (MaxAddress < SIZE_16TB) {
682 TCR |= TCR_IPS_16TB;
683 } else if (MaxAddress < SIZE_256TB) {
684 TCR |= TCR_IPS_256TB;
685 } else {
686 DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
687 ASSERT (0); // Bigger than 48-bit memory space are not supported
688 return RETURN_UNSUPPORTED;
689 }
690 } else {
691 ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
692 return RETURN_UNSUPPORTED;
693 }
694
695 // Set TCR
696 ArmSetTCR (TCR);
697
698 // Allocate pages for translation table
699 TranslationTablePageCount = EFI_SIZE_TO_PAGES(RootTableEntryCount * sizeof(UINT64));
700 TranslationTable = (UINT64*)AllocateAlignedPages (TranslationTablePageCount, TT_ALIGNMENT_DESCRIPTION_TABLE);
701 if (TranslationTable == NULL) {
702 return RETURN_OUT_OF_RESOURCES;
703 }
704 // We set TTBR0 just after allocating the table to retrieve its location from the subsequent
705 // functions without needing to pass this value across the functions. The MMU is only enabled
706 // after the translation tables are populated.
707 ArmSetTTBR0 (TranslationTable);
708
709 if (TranslationTableBase != NULL) {
710 *TranslationTableBase = TranslationTable;
711 }
712
713 if (TranslationTableSize != NULL) {
714 *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);
715 }
716
717 ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
718
719 // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
720 ArmDisableMmu ();
721 ArmDisableDataCache ();
722 ArmDisableInstructionCache ();
723
724 // Make sure nothing sneaked into the cache
725 ArmCleanInvalidateDataCache ();
726 ArmInvalidateInstructionCache ();
727
728 TranslationTableAttribute = TT_ATTR_INDX_INVALID;
729 while (MemoryTable->Length != 0) {
730 // Find the memory attribute for the Translation Table
731 if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) &&
732 ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
733 TranslationTableAttribute = MemoryTable->Attributes;
734 }
735
736 Status = FillTranslationTable (TranslationTable, MemoryTable);
737 if (RETURN_ERROR (Status)) {
738 goto FREE_TRANSLATION_TABLE;
739 }
740 MemoryTable++;
741 }
742
743 // Translate the Memory Attributes into Translation Table Register Attributes
744 if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
745 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
746 TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE | TCR_RGN_INNER_NON_CACHEABLE;
747 } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
748 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
749 TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC | TCR_RGN_INNER_WRITE_BACK_ALLOC;
750 } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
751 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
752 TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH | TCR_RGN_INNER_WRITE_THROUGH;
753 } else {
754 // If we failed to find a mapping that contains the root translation table then it probably means the translation table
755 // is not mapped in the given memory map.
756 ASSERT (0);
757 Status = RETURN_UNSUPPORTED;
758 goto FREE_TRANSLATION_TABLE;
759 }
760
761 // Set again TCR after getting the Translation Table attributes
762 ArmSetTCR (TCR);
763
764 ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC
765 MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC
766 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT
767 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)); // mapped to EFI_MEMORY_WB
768
769 ArmDisableAlignmentCheck ();
770 ArmEnableInstructionCache ();
771 ArmEnableDataCache ();
772
773 ArmEnableMmu ();
774 return RETURN_SUCCESS;
775
776 FREE_TRANSLATION_TABLE:
777 FreePages (TranslationTable, TranslationTablePageCount);
778 return Status;
779 }
EFI Development Kit II mirror for PVE