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ArmPkg/AArch64Mmu: remove unused GcdAttributeToArmAttribute()
[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Mmu.c
1 /** @file
2 * File managing the MMU for ARMv8 architecture
3 *
4 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16 #include <Uefi.h>
17 #include <Chipset/AArch64.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/MemoryAllocationLib.h>
20 #include <Library/ArmLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/DebugLib.h>
23 #include "AArch64Lib.h"
24 #include "ArmLibPrivate.h"
25
26 // We use this index definition to define an invalid block entry
27 #define TT_ATTR_INDX_INVALID ((UINT32)~0)
28
29 STATIC
30 UINT64
31 ArmMemoryAttributeToPageAttribute (
32 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
33 )
34 {
35 switch (Attributes) {
36 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
37 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
38 return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
39
40 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
41 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
42 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
43
44 // Uncached and device mappings are treated as outer shareable by default,
45 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
46 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
47 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
48
49 default:
50 ASSERT(0);
51 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
52 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
53 return TT_ATTR_INDX_DEVICE_MEMORY;
54 }
55 }
56
57 UINT64
58 PageAttributeToGcdAttribute (
59 IN UINT64 PageAttributes
60 )
61 {
62 UINT64 GcdAttributes;
63
64 switch (PageAttributes & TT_ATTR_INDX_MASK) {
65 case TT_ATTR_INDX_DEVICE_MEMORY:
66 GcdAttributes = EFI_MEMORY_UC;
67 break;
68 case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
69 GcdAttributes = EFI_MEMORY_WC;
70 break;
71 case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
72 GcdAttributes = EFI_MEMORY_WT;
73 break;
74 case TT_ATTR_INDX_MEMORY_WRITE_BACK:
75 GcdAttributes = EFI_MEMORY_WB;
76 break;
77 default:
78 DEBUG ((EFI_D_ERROR, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes));
79 ASSERT (0);
80 // The Global Coherency Domain (GCD) value is defined as a bit set.
81 // Returning 0 means no attribute has been set.
82 GcdAttributes = 0;
83 }
84
85 // Determine protection attributes
86 if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
87 // Read only cases map to write-protect
88 GcdAttributes |= EFI_MEMORY_WP;
89 }
90
91 // Process eXecute Never attribute
92 if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0 ) {
93 GcdAttributes |= EFI_MEMORY_XP;
94 }
95
96 return GcdAttributes;
97 }
98
99 ARM_MEMORY_REGION_ATTRIBUTES
100 GcdAttributeToArmAttribute (
101 IN UINT64 GcdAttributes
102 )
103 {
104 switch (GcdAttributes & 0xFF) {
105 case EFI_MEMORY_UC:
106 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
107 case EFI_MEMORY_WC:
108 return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
109 case EFI_MEMORY_WT:
110 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
111 case EFI_MEMORY_WB:
112 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
113 default:
114 DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes));
115 ASSERT (0);
116 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
117 }
118 }
119
120 // Describe the T0SZ values for each translation table level
121 typedef struct {
122 UINTN MinT0SZ;
123 UINTN MaxT0SZ;
124 UINTN LargestT0SZ; // Generally (MaxT0SZ == LargestT0SZ) but at the Level3 Table
125 // the MaxT0SZ is not at the boundary of the table
126 } T0SZ_DESCRIPTION_PER_LEVEL;
127
128 // Map table for the corresponding Level of Table
129 STATIC CONST T0SZ_DESCRIPTION_PER_LEVEL T0SZPerTableLevel[] = {
130 { 16, 24, 24 }, // Table Level 0
131 { 25, 33, 33 }, // Table Level 1
132 { 34, 39, 42 } // Table Level 2
133 };
134
135 VOID
136 GetRootTranslationTableInfo (
137 IN UINTN T0SZ,
138 OUT UINTN *TableLevel,
139 OUT UINTN *TableEntryCount
140 )
141 {
142 UINTN Index;
143
144 // Identify the level of the root table from the given T0SZ
145 for (Index = 0; Index < sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL); Index++) {
146 if (T0SZ <= T0SZPerTableLevel[Index].MaxT0SZ) {
147 break;
148 }
149 }
150
151 // If we have not found the corresponding maximum T0SZ then we use the last one
152 if (Index == sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL)) {
153 Index--;
154 }
155
156 // Get the level of the root table
157 if (TableLevel) {
158 *TableLevel = Index;
159 }
160
161 // The Size of the Table is 2^(T0SZ-LargestT0SZ)
162 if (TableEntryCount) {
163 *TableEntryCount = 1 << (T0SZPerTableLevel[Index].LargestT0SZ - T0SZ + 1);
164 }
165 }
166
167 STATIC
168 VOID
169 LookupAddresstoRootTable (
170 IN UINT64 MaxAddress,
171 OUT UINTN *T0SZ,
172 OUT UINTN *TableEntryCount
173 )
174 {
175 UINTN TopBit;
176
177 // Check the parameters are not NULL
178 ASSERT ((T0SZ != NULL) && (TableEntryCount != NULL));
179
180 // Look for the highest bit set in MaxAddress
181 for (TopBit = 63; TopBit != 0; TopBit--) {
182 if ((1ULL << TopBit) & MaxAddress) {
183 // MaxAddress top bit is found
184 TopBit = TopBit + 1;
185 break;
186 }
187 }
188 ASSERT (TopBit != 0);
189
190 // Calculate T0SZ from the top bit of the MaxAddress
191 *T0SZ = 64 - TopBit;
192
193 // Get the Table info from T0SZ
194 GetRootTranslationTableInfo (*T0SZ, NULL, TableEntryCount);
195 }
196
197 STATIC
198 UINT64*
199 GetBlockEntryListFromAddress (
200 IN UINT64 *RootTable,
201 IN UINT64 RegionStart,
202 OUT UINTN *TableLevel,
203 IN OUT UINT64 *BlockEntrySize,
204 OUT UINT64 **LastBlockEntry
205 )
206 {
207 UINTN RootTableLevel;
208 UINTN RootTableEntryCount;
209 UINT64 *TranslationTable;
210 UINT64 *BlockEntry;
211 UINT64 *SubTableBlockEntry;
212 UINT64 BlockEntryAddress;
213 UINTN BaseAddressAlignment;
214 UINTN PageLevel;
215 UINTN Index;
216 UINTN IndexLevel;
217 UINTN T0SZ;
218 UINT64 Attributes;
219 UINT64 TableAttributes;
220
221 // Initialize variable
222 BlockEntry = NULL;
223
224 // Ensure the parameters are valid
225 if (!(TableLevel && BlockEntrySize && LastBlockEntry)) {
226 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
227 return NULL;
228 }
229
230 // Ensure the Region is aligned on 4KB boundary
231 if ((RegionStart & (SIZE_4KB - 1)) != 0) {
232 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
233 return NULL;
234 }
235
236 // Ensure the required size is aligned on 4KB boundary and not 0
237 if ((*BlockEntrySize & (SIZE_4KB - 1)) != 0 || *BlockEntrySize == 0) {
238 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
239 return NULL;
240 }
241
242 T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
243 // Get the Table info from T0SZ
244 GetRootTranslationTableInfo (T0SZ, &RootTableLevel, &RootTableEntryCount);
245
246 // If the start address is 0x0 then we use the size of the region to identify the alignment
247 if (RegionStart == 0) {
248 // Identify the highest possible alignment for the Region Size
249 BaseAddressAlignment = LowBitSet64 (*BlockEntrySize);
250 } else {
251 // Identify the highest possible alignment for the Base Address
252 BaseAddressAlignment = LowBitSet64 (RegionStart);
253 }
254
255 // Identify the Page Level the RegionStart must belong to. Note that PageLevel
256 // should be at least 1 since block translations are not supported at level 0
257 PageLevel = MAX (3 - ((BaseAddressAlignment - 12) / 9), 1);
258
259 // If the required size is smaller than the current block size then we need to go to the page below.
260 // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment
261 // of the allocation size
262 while (*BlockEntrySize < TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel)) {
263 // It does not fit so we need to go a page level above
264 PageLevel++;
265 }
266
267 //
268 // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries
269 //
270
271 TranslationTable = RootTable;
272 for (IndexLevel = RootTableLevel; IndexLevel <= PageLevel; IndexLevel++) {
273 BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel, RegionStart);
274
275 if ((IndexLevel != 3) && ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {
276 // Go to the next table
277 TranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
278
279 // If we are at the last level then update the last level to next level
280 if (IndexLevel == PageLevel) {
281 // Enter the next level
282 PageLevel++;
283 }
284 } else if ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) {
285 // If we are not at the last level then we need to split this BlockEntry
286 if (IndexLevel != PageLevel) {
287 // Retrieve the attributes from the block entry
288 Attributes = *BlockEntry & TT_ATTRIBUTES_MASK;
289
290 // Convert the block entry attributes into Table descriptor attributes
291 TableAttributes = TT_TABLE_AP_NO_PERMISSION;
292 if (Attributes & TT_PXN_MASK) {
293 TableAttributes = TT_TABLE_PXN;
294 }
295 // XN maps to UXN in the EL1&0 translation regime
296 if (Attributes & TT_XN_MASK) {
297 TableAttributes = TT_TABLE_XN;
298 }
299 if (Attributes & TT_NS) {
300 TableAttributes = TT_TABLE_NS;
301 }
302
303 // Get the address corresponding at this entry
304 BlockEntryAddress = RegionStart;
305 BlockEntryAddress = BlockEntryAddress >> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
306 // Shift back to right to set zero before the effective address
307 BlockEntryAddress = BlockEntryAddress << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
308
309 // Set the correct entry type for the next page level
310 if ((IndexLevel + 1) == 3) {
311 Attributes |= TT_TYPE_BLOCK_ENTRY_LEVEL3;
312 } else {
313 Attributes |= TT_TYPE_BLOCK_ENTRY;
314 }
315
316 // Create a new translation table
317 TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);
318 if (TranslationTable == NULL) {
319 return NULL;
320 }
321
322 // Populate the newly created lower level table
323 SubTableBlockEntry = TranslationTable;
324 for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
325 *SubTableBlockEntry = Attributes | (BlockEntryAddress + (Index << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel + 1)));
326 SubTableBlockEntry++;
327 }
328
329 // Fill the BlockEntry with the new TranslationTable
330 *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY;
331 }
332 } else {
333 if (IndexLevel != PageLevel) {
334 //
335 // Case when we have an Invalid Entry and we are at a page level above of the one targetted.
336 //
337
338 // Create a new translation table
339 TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE);
340 if (TranslationTable == NULL) {
341 return NULL;
342 }
343
344 ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64));
345
346 // Fill the new BlockEntry with the TranslationTable
347 *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;
348 }
349 }
350 }
351
352 // Expose the found PageLevel to the caller
353 *TableLevel = PageLevel;
354
355 // Now, we have the Table Level we can get the Block Size associated to this table
356 *BlockEntrySize = TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel);
357
358 // The last block of the root table depends on the number of entry in this table,
359 // otherwise it is always the (TT_ENTRY_COUNT - 1)th entry in the table.
360 *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable,
361 (PageLevel == RootTableLevel) ? RootTableEntryCount : TT_ENTRY_COUNT);
362
363 return BlockEntry;
364 }
365
366 STATIC
367 RETURN_STATUS
368 UpdateRegionMapping (
369 IN UINT64 *RootTable,
370 IN UINT64 RegionStart,
371 IN UINT64 RegionLength,
372 IN UINT64 Attributes,
373 IN UINT64 BlockEntryMask
374 )
375 {
376 UINT32 Type;
377 UINT64 *BlockEntry;
378 UINT64 *LastBlockEntry;
379 UINT64 BlockEntrySize;
380 UINTN TableLevel;
381
382 // Ensure the Length is aligned on 4KB boundary
383 if ((RegionLength == 0) || ((RegionLength & (SIZE_4KB - 1)) != 0)) {
384 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
385 return RETURN_INVALID_PARAMETER;
386 }
387
388 do {
389 // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor
390 // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
391 BlockEntrySize = RegionLength;
392 BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);
393 if (BlockEntry == NULL) {
394 // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables
395 return RETURN_OUT_OF_RESOURCES;
396 }
397
398 if (TableLevel != 3) {
399 Type = TT_TYPE_BLOCK_ENTRY;
400 } else {
401 Type = TT_TYPE_BLOCK_ENTRY_LEVEL3;
402 }
403
404 do {
405 // Fill the Block Entry with attribute and output block address
406 *BlockEntry &= BlockEntryMask;
407 *BlockEntry |= (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type;
408
409 // Go to the next BlockEntry
410 RegionStart += BlockEntrySize;
411 RegionLength -= BlockEntrySize;
412 BlockEntry++;
413
414 // Break the inner loop when next block is a table
415 // Rerun GetBlockEntryListFromAddress to avoid page table memory leak
416 if (TableLevel != 3 &&
417 (*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
418 break;
419 }
420 } while ((RegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry));
421 } while (RegionLength != 0);
422
423 return RETURN_SUCCESS;
424 }
425
426 STATIC
427 RETURN_STATUS
428 FillTranslationTable (
429 IN UINT64 *RootTable,
430 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
431 )
432 {
433 return UpdateRegionMapping (
434 RootTable,
435 MemoryRegion->VirtualBase,
436 MemoryRegion->Length,
437 ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF,
438 0
439 );
440 }
441
442 RETURN_STATUS
443 SetMemoryAttributes (
444 IN EFI_PHYSICAL_ADDRESS BaseAddress,
445 IN UINT64 Length,
446 IN UINT64 Attributes,
447 IN EFI_PHYSICAL_ADDRESS VirtualMask
448 )
449 {
450 RETURN_STATUS Status;
451 ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion;
452 UINT64 *TranslationTable;
453
454 MemoryRegion.PhysicalBase = BaseAddress;
455 MemoryRegion.VirtualBase = BaseAddress;
456 MemoryRegion.Length = Length;
457 MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes);
458
459 TranslationTable = ArmGetTTBR0BaseAddress ();
460
461 Status = FillTranslationTable (TranslationTable, &MemoryRegion);
462 if (RETURN_ERROR (Status)) {
463 return Status;
464 }
465
466 // Invalidate all TLB entries so changes are synced
467 ArmInvalidateTlb ();
468
469 return RETURN_SUCCESS;
470 }
471
472 STATIC
473 RETURN_STATUS
474 SetMemoryRegionAttribute (
475 IN EFI_PHYSICAL_ADDRESS BaseAddress,
476 IN UINT64 Length,
477 IN UINT64 Attributes,
478 IN UINT64 BlockEntryMask
479 )
480 {
481 RETURN_STATUS Status;
482 UINT64 *RootTable;
483
484 RootTable = ArmGetTTBR0BaseAddress ();
485
486 Status = UpdateRegionMapping (RootTable, BaseAddress, Length, Attributes, BlockEntryMask);
487 if (RETURN_ERROR (Status)) {
488 return Status;
489 }
490
491 // Invalidate all TLB entries so changes are synced
492 ArmInvalidateTlb ();
493
494 return RETURN_SUCCESS;
495 }
496
497 RETURN_STATUS
498 ArmSetMemoryRegionNoExec (
499 IN EFI_PHYSICAL_ADDRESS BaseAddress,
500 IN UINT64 Length
501 )
502 {
503 UINT64 Val;
504
505 if (ArmReadCurrentEL () == AARCH64_EL1) {
506 Val = TT_PXN_MASK | TT_UXN_MASK;
507 } else {
508 Val = TT_XN_MASK;
509 }
510
511 return SetMemoryRegionAttribute (
512 BaseAddress,
513 Length,
514 Val,
515 ~TT_ADDRESS_MASK_BLOCK_ENTRY);
516 }
517
518 RETURN_STATUS
519 ArmClearMemoryRegionNoExec (
520 IN EFI_PHYSICAL_ADDRESS BaseAddress,
521 IN UINT64 Length
522 )
523 {
524 UINT64 Mask;
525
526 // XN maps to UXN in the EL1&0 translation regime
527 Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);
528
529 return SetMemoryRegionAttribute (
530 BaseAddress,
531 Length,
532 0,
533 Mask);
534 }
535
536 RETURN_STATUS
537 ArmSetMemoryRegionReadOnly (
538 IN EFI_PHYSICAL_ADDRESS BaseAddress,
539 IN UINT64 Length
540 )
541 {
542 return SetMemoryRegionAttribute (
543 BaseAddress,
544 Length,
545 TT_AP_RO_RO,
546 ~TT_ADDRESS_MASK_BLOCK_ENTRY);
547 }
548
549 RETURN_STATUS
550 ArmClearMemoryRegionReadOnly (
551 IN EFI_PHYSICAL_ADDRESS BaseAddress,
552 IN UINT64 Length
553 )
554 {
555 return SetMemoryRegionAttribute (
556 BaseAddress,
557 Length,
558 TT_AP_NO_RO,
559 ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));
560 }
561
562 RETURN_STATUS
563 EFIAPI
564 ArmConfigureMmu (
565 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
566 OUT VOID **TranslationTableBase OPTIONAL,
567 OUT UINTN *TranslationTableSize OPTIONAL
568 )
569 {
570 VOID* TranslationTable;
571 UINTN TranslationTablePageCount;
572 UINT32 TranslationTableAttribute;
573 ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry;
574 UINT64 MaxAddress;
575 UINT64 TopAddress;
576 UINTN T0SZ;
577 UINTN RootTableEntryCount;
578 UINT64 TCR;
579 RETURN_STATUS Status;
580
581 if(MemoryTable == NULL) {
582 ASSERT (MemoryTable != NULL);
583 return RETURN_INVALID_PARAMETER;
584 }
585
586 // Identify the highest address of the memory table
587 MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1;
588 MemoryTableEntry = MemoryTable;
589 while (MemoryTableEntry->Length != 0) {
590 TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1;
591 if (TopAddress > MaxAddress) {
592 MaxAddress = TopAddress;
593 }
594 MemoryTableEntry++;
595 }
596
597 // Lookup the Table Level to get the information
598 LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);
599
600 //
601 // Set TCR that allows us to retrieve T0SZ in the subsequent functions
602 //
603 // Ideally we will be running at EL2, but should support EL1 as well.
604 // UEFI should not run at EL3.
605 if (ArmReadCurrentEL () == AARCH64_EL2) {
606 //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
607 TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
608
609 // Set the Physical Address Size using MaxAddress
610 if (MaxAddress < SIZE_4GB) {
611 TCR |= TCR_PS_4GB;
612 } else if (MaxAddress < SIZE_64GB) {
613 TCR |= TCR_PS_64GB;
614 } else if (MaxAddress < SIZE_1TB) {
615 TCR |= TCR_PS_1TB;
616 } else if (MaxAddress < SIZE_4TB) {
617 TCR |= TCR_PS_4TB;
618 } else if (MaxAddress < SIZE_16TB) {
619 TCR |= TCR_PS_16TB;
620 } else if (MaxAddress < SIZE_256TB) {
621 TCR |= TCR_PS_256TB;
622 } else {
623 DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
624 ASSERT (0); // Bigger than 48-bit memory space are not supported
625 return RETURN_UNSUPPORTED;
626 }
627 } else if (ArmReadCurrentEL () == AARCH64_EL1) {
628 TCR = T0SZ | TCR_TG0_4KB;
629
630 // Set the Physical Address Size using MaxAddress
631 if (MaxAddress < SIZE_4GB) {
632 TCR |= TCR_IPS_4GB;
633 } else if (MaxAddress < SIZE_64GB) {
634 TCR |= TCR_IPS_64GB;
635 } else if (MaxAddress < SIZE_1TB) {
636 TCR |= TCR_IPS_1TB;
637 } else if (MaxAddress < SIZE_4TB) {
638 TCR |= TCR_IPS_4TB;
639 } else if (MaxAddress < SIZE_16TB) {
640 TCR |= TCR_IPS_16TB;
641 } else if (MaxAddress < SIZE_256TB) {
642 TCR |= TCR_IPS_256TB;
643 } else {
644 DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
645 ASSERT (0); // Bigger than 48-bit memory space are not supported
646 return RETURN_UNSUPPORTED;
647 }
648 } else {
649 ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
650 return RETURN_UNSUPPORTED;
651 }
652
653 // Set TCR
654 ArmSetTCR (TCR);
655
656 // Allocate pages for translation table
657 TranslationTablePageCount = EFI_SIZE_TO_PAGES(RootTableEntryCount * sizeof(UINT64));
658 TranslationTable = (UINT64*)AllocateAlignedPages (TranslationTablePageCount, TT_ALIGNMENT_DESCRIPTION_TABLE);
659 if (TranslationTable == NULL) {
660 return RETURN_OUT_OF_RESOURCES;
661 }
662 // We set TTBR0 just after allocating the table to retrieve its location from the subsequent
663 // functions without needing to pass this value across the functions. The MMU is only enabled
664 // after the translation tables are populated.
665 ArmSetTTBR0 (TranslationTable);
666
667 if (TranslationTableBase != NULL) {
668 *TranslationTableBase = TranslationTable;
669 }
670
671 if (TranslationTableSize != NULL) {
672 *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);
673 }
674
675 ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
676
677 // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
678 ArmDisableMmu ();
679 ArmDisableDataCache ();
680 ArmDisableInstructionCache ();
681
682 // Make sure nothing sneaked into the cache
683 ArmCleanInvalidateDataCache ();
684 ArmInvalidateInstructionCache ();
685
686 TranslationTableAttribute = TT_ATTR_INDX_INVALID;
687 while (MemoryTable->Length != 0) {
688 // Find the memory attribute for the Translation Table
689 if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) &&
690 ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
691 TranslationTableAttribute = MemoryTable->Attributes;
692 }
693
694 Status = FillTranslationTable (TranslationTable, MemoryTable);
695 if (RETURN_ERROR (Status)) {
696 goto FREE_TRANSLATION_TABLE;
697 }
698 MemoryTable++;
699 }
700
701 // Translate the Memory Attributes into Translation Table Register Attributes
702 if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
703 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
704 TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE | TCR_RGN_INNER_NON_CACHEABLE;
705 } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
706 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
707 TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC | TCR_RGN_INNER_WRITE_BACK_ALLOC;
708 } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
709 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
710 TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH | TCR_RGN_INNER_WRITE_THROUGH;
711 } else {
712 // If we failed to find a mapping that contains the root translation table then it probably means the translation table
713 // is not mapped in the given memory map.
714 ASSERT (0);
715 Status = RETURN_UNSUPPORTED;
716 goto FREE_TRANSLATION_TABLE;
717 }
718
719 // Set again TCR after getting the Translation Table attributes
720 ArmSetTCR (TCR);
721
722 ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC
723 MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC
724 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT
725 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)); // mapped to EFI_MEMORY_WB
726
727 ArmDisableAlignmentCheck ();
728 ArmEnableInstructionCache ();
729 ArmEnableDataCache ();
730
731 ArmEnableMmu ();
732 return RETURN_SUCCESS;
733
734 FREE_TRANSLATION_TABLE:
735 FreePages (TranslationTable, TranslationTablePageCount);
736 return Status;
737 }
EFI Development Kit II mirror for PVE