1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
7 # SPDX-License-Identifier: BSD-2-Clause-Patent
9 #------------------------------------------------------------------------------
11 #include <AsmMacroIoLib.h>
15 .set CTRL_M_BIT, (1 << 0)
16 .set CTRL_C_BIT, (1 << 2)
17 .set CTRL_B_BIT, (1 << 7)
18 .set CTRL_I_BIT, (1 << 12)
21 ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
22 mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
25 ASM_FUNC(ArmCleanDataCacheEntryByMVA)
26 mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
30 ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
31 mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU
34 ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
35 mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU
36 mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor
39 ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
40 mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
44 ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)
45 mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
49 ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)
50 mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
54 ASM_FUNC(ArmCleanDataCacheEntryBySetWay)
55 mcr p15, 0, r0, c7, c10, 2 @ Clean this line
58 ASM_FUNC(ArmInvalidateInstructionCache)
59 mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
64 ASM_FUNC(ArmEnableMmu)
73 ASM_FUNC(ArmDisableMmu)
76 mcr p15,0,R0,c1,c0,0 @Disable MMU
78 mcr p15,0,R0,c8,c7,0 @Invalidate TLB
79 mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
84 ASM_FUNC(ArmDisableCachesAndMmu)
85 mrc p15, 0, r0, c1, c0, 0 @ Get control register
86 bic r0, r0, #CTRL_M_BIT @ Disable MMU
87 bic r0, r0, #CTRL_C_BIT @ Disable D Cache
88 bic r0, r0, #CTRL_I_BIT @ Disable I Cache
89 mcr p15, 0, r0, c1, c0, 0 @ Write control register
94 ASM_FUNC(ArmMmuEnabled)
99 ASM_FUNC(ArmEnableDataCache)
101 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
102 orr R0,R0,R1 @Set C bit
103 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
108 ASM_FUNC(ArmDisableDataCache)
110 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
111 bic R0,R0,R1 @Clear C bit
112 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
117 ASM_FUNC(ArmEnableInstructionCache)
119 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
120 orr R0,R0,R1 @Set I bit
121 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
126 ASM_FUNC(ArmDisableInstructionCache)
128 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
129 bic R0,R0,R1 @Clear I bit.
130 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
135 ASM_FUNC(ArmEnableSWPInstruction)
136 mrc p15, 0, r0, c1, c0, 0
137 orr r0, r0, #0x00000400
138 mcr p15, 0, r0, c1, c0, 0
142 ASM_FUNC(ArmEnableBranchPrediction)
143 mrc p15, 0, r0, c1, c0, 0
144 orr r0, r0, #0x00000800
145 mcr p15, 0, r0, c1, c0, 0
150 ASM_FUNC(ArmDisableBranchPrediction)
151 mrc p15, 0, r0, c1, c0, 0
152 bic r0, r0, #0x00000800
153 mcr p15, 0, r0, c1, c0, 0
158 ASM_FUNC(ArmSetLowVectors)
159 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
160 bic r0, r0, #0x00002000 @ clear V bit
161 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
165 ASM_FUNC(ArmSetHighVectors)
166 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
167 orr r0, r0, #0x00002000 @ Set V bit
168 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
172 ASM_FUNC(ArmV7AllDataCachesOperation)
173 stmfd SP!,{r4-r12, LR}
174 mov R1, R0 @ Save Function call in R1
175 mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
176 ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
177 mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
182 add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
183 mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
184 and R12, R12, #7 @ get those 3 bits alone
186 blt L_Skip @ no cache or only instruction cache at this level
187 mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
188 isb @ isb to sync the change to the CacheSizeID reg
189 mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
190 and R2, R12, #0x7 @ extract the line length field
191 add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
195 ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
196 clz R5, R4 @ R5 is the bit position of the way size increment
197 @ ldr R7, =0x00007FFF
200 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
203 mov R9, R4 @ R9 working copy of the max way size (right aligned)
206 orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
207 orr R0, R0, R7, LSL R2 @ factor in the index number
211 subs R9, R9, #1 @ decrement the way number
213 subs R7, R7, #1 @ decrement the index
216 add R10, R10, #2 @ increment the cache number
222 ldmfd SP!, {r4-r12, lr}
225 ASM_FUNC(ArmDataMemoryBarrier)
229 ASM_FUNC(ArmDataSynchronizationBarrier)
233 ASM_FUNC(ArmInstructionSynchronizationBarrier)
237 ASM_FUNC(ArmReadVBar)
238 # Set the Address of the Vector Table in the VBAR register
239 mrc p15, 0, r0, c12, c0, 0
242 ASM_FUNC(ArmWriteVBar)
243 # Set the Address of the Vector Table in the VBAR register
244 mcr p15, 0, r0, c12, c0, 0
245 # Ensure the SCTLR.V bit is clear
246 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
247 bic r0, r0, #0x00002000 @ clear V bit
248 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
252 ASM_FUNC(ArmEnableVFP)
253 # Read CPACR (Coprocessor Access Control Register)
254 mrc p15, 0, r0, c1, c0, 2
255 # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
256 orr r0, r0, #0x00f00000
257 # Write back CPACR (Coprocessor Access Control Register)
258 mcr p15, 0, r0, c1, c0, 2
260 # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
263 mcr p10,#0x7,r0,c8,c0,#0
265 # Set the FPU model so Clang does not choke on the next instruction
275 #Note: Return 0 in Uniprocessor implementation
276 ASM_FUNC(ArmReadCbar)
277 mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
280 ASM_FUNC(ArmReadMpidr)
281 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
284 ASM_FUNC(ArmReadTpidrurw)
285 mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
288 ASM_FUNC(ArmWriteTpidrurw)
289 mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
292 ASM_FUNC(ArmIsArchTimerImplemented)
293 mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1
294 and r0, r0, #0x000F0000
297 ASM_FUNC(ArmReadIdPfr1)
298 mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register
301 ASM_FUNCTION_REMOVE_IF_UNREFERENCED