1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 # All rights reserved. This program and the accompanying materials
6 # are licensed and made available under the terms and conditions of the BSD License
7 # which accompanies this distribution. The full text of the license may be found at
8 # http://opensource.org/licenses/bsd-license.php
10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #------------------------------------------------------------------------------
17 .globl ASM_PFX(ArmCleanInvalidateDataCache)
18 .globl ASM_PFX(ArmCleanDataCache)
19 .globl ASM_PFX(ArmInvalidateDataCache)
20 .globl ASM_PFX(ArmInvalidateInstructionCache)
21 .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
22 .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
23 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
24 .globl ASM_PFX(ArmEnableMmu)
25 .globl ASM_PFX(ArmDisableMmu)
26 .globl ASM_PFX(ArmMmuEnabled)
27 .globl ASM_PFX(ArmEnableDataCache)
28 .globl ASM_PFX(ArmDisableDataCache)
29 .globl ASM_PFX(ArmEnableInstructionCache)
30 .globl ASM_PFX(ArmDisableInstructionCache)
31 .globl ASM_PFX(ArmEnableBranchPrediction)
32 .globl ASM_PFX(ArmDisableBranchPrediction)
38 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
39 mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
43 ASM_PFX(ArmCleanDataCacheEntryByMVA):
44 mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
48 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
49 mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
53 ASM_PFX(ArmCleanDataCache):
54 mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache
58 ASM_PFX(ArmCleanInvalidateDataCache):
59 mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache
63 ASM_PFX(ArmInvalidateDataCache):
64 mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache
68 ASM_PFX(ArmInvalidateInstructionCache):
69 mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache
71 mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
74 ASM_PFX(ArmEnableMmu):
80 ASM_PFX(ArmMmuEnabled):
85 ASM_PFX(ArmDisableMmu):
90 mcr p15,0,R0,c7,c10,4 @Data synchronization barrier
92 mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer
95 ASM_PFX(ArmEnableDataCache):
97 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
98 orr R0,R0,R1 @Set C bit
99 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
102 ASM_PFX(ArmDisableDataCache):
104 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
105 bic R0,R0,R1 @Clear C bit
106 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
109 ASM_PFX(ArmEnableInstructionCache):
111 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
112 orr R0,R0,R1 @Set I bit
113 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
116 ASM_PFX(ArmDisableInstructionCache):
118 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
119 bic R0,R0,R1 @Clear I bit.
120 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
123 ASM_PFX(ArmEnableBranchPrediction):
124 mrc p15, 0, r0, c1, c0, 0
125 orr r0, r0, #0x00000800
126 mcr p15, 0, r0, c1, c0, 0
129 ASM_PFX(ArmDisableBranchPrediction):
130 mrc p15, 0, r0, c1, c0, 0
131 bic r0, r0, #0x00000800
132 mcr p15, 0, r0, c1, c0, 0
135 ASM_FUNCTION_REMOVE_IF_UNREFERENCED