ArmPkg/Library/ArmLib/Arm11/Arm11Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18 .text
  19 .align 2
  20 GCC_ASM_EXPORT(ArmDisableCachesAndMmu)
  21 GCC_ASM_EXPORT(ArmInvalidateInstructionAndDataTlb)
  22 GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
  23 GCC_ASM_EXPORT(ArmCleanDataCache)
  24 GCC_ASM_EXPORT(ArmInvalidateDataCache)
  25 GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
  26 GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
  27 GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
  28 GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
  29 GCC_ASM_EXPORT(ArmEnableMmu)
  30 GCC_ASM_EXPORT(ArmDisableMmu)
  31 GCC_ASM_EXPORT(ArmMmuEnabled)
  32 GCC_ASM_EXPORT(ArmEnableDataCache)
  33 GCC_ASM_EXPORT(ArmDisableDataCache)
  34 GCC_ASM_EXPORT(ArmEnableInstructionCache)
  35 GCC_ASM_EXPORT(ArmDisableInstructionCache)
  36 GCC_ASM_EXPORT(ArmEnableBranchPrediction)
  37 GCC_ASM_EXPORT(ArmDisableBranchPrediction)
  38 GCC_ASM_EXPORT(ArmDataMemoryBarrier)
  39 GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
  40 GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
  41 GCC_ASM_EXPORT(ArmSetLowVectors)
  42 GCC_ASM_EXPORT(ArmSetHighVectors)
  43 GCC_ASM_EXPORT(ArmIsMpCore)
  44 GCC_ASM_EXPORT(ArmCallWFI)
  45 GCC_ASM_EXPORT(ArmReadMpidr)
  46 GCC_ASM_EXPORT(ArmReadMidr)
  47 GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
  48 GCC_ASM_EXPORT(ArmEnableFiq)
  49 GCC_ASM_EXPORT(ArmDisableFiq)
  50 GCC_ASM_EXPORT(ArmEnableInterrupts)
  51 GCC_ASM_EXPORT(ArmDisableInterrupts)
  52 GCC_ASM_EXPORT (ArmEnableVFP)
  53
  54 Arm11PartNumberMask:  .word       0xFFF0
  55 Arm11PartNumber:      .word           0xB020
  56
  57 .set DC_ON, (0x1<<2)
  58 .set IC_ON, (0x1<<12)
  59 .set XP_ON, (0x1<<23)
  60 .set CTRL_M_BIT,  (1 << 0)
  61 .set CTRL_C_BIT,  (1 << 2)
  62 .set CTRL_I_BIT,  (1 << 12)
  63
  64 ASM_PFX(ArmDisableCachesAndMmu):
  65   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
  66   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
  67   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
  68   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
  69   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
  70   bx      LR
  71
  72 ASM_PFX(ArmInvalidateInstructionAndDataTlb):
  73   mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB
  74   bx lr
  75
  76 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  77   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  78   bx      lr
  79
  80
  81 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  82   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  83   bx      lr
  84
  85
  86 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  87   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  88   bx      lr
  89
  90
  91 ASM_PFX(ArmCleanDataCache):
  92   mcr     p15, 0, r0, c7, c10, 0  @ clean entire data cache
  93   bx      lr
  94
  95
  96 ASM_PFX(ArmCleanInvalidateDataCache):
  97   mcr     p15, 0, r0, c7, c14, 0  @ clean and invalidate entire data cache
  98   bx      lr
  99
 100
 101 ASM_PFX(ArmInvalidateDataCache):
 102   mcr     p15, 0, r0, c7, c6, 0  @ invalidate entire data cache
 103   bx      lr
 104
 105
 106 ASM_PFX(ArmInvalidateInstructionCache):
 107   mcr     p15, 0, r0, c7, c5, 0  @invalidate entire instruction cache
 108   mov     R0,#0
 109   mcr     p15,0,R0,c7,c5,4       @Flush Prefetch buffer
 110   bx      lr
 111
 112 ASM_PFX(ArmEnableMmu):
 113   mrc     p15,0,R0,c1,c0,0
 114   orr     R0,R0,#1
 115   mcr     p15,0,R0,c1,c0,0
 116   bx      LR
 117
 118 ASM_PFX(ArmMmuEnabled):
 119   mrc     p15,0,R0,c1,c0,0
 120   and     R0,R0,#1
 121   bx      LR
 122
 123 ASM_PFX(ArmDisableMmu):
 124   mrc     p15,0,R0,c1,c0,0
 125   bic     R0,R0,#1
 126   mcr     p15,0,R0,c1,c0,0
 127   mov     R0,#0
 128   mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
 129   mov     R0,#0
 130   mcr     p15,0,R0,c7,c5,4      @Flush Prefetch buffer
 131   bx      LR
 132
 133 ASM_PFX(ArmEnableDataCache):
 134   LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON
 135   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 136   orr     R0,R0,R1              @Set C bit
 137   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 138   bx      LR
 139
 140 ASM_PFX(ArmDisableDataCache):
 141   LoadConstantToReg(DC_ON, R1)  @ldr     R1,=DC_ON
 142   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 143   bic     R0,R0,R1              @Clear C bit
 144   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 145   bx      LR
 146
 147 ASM_PFX(ArmEnableInstructionCache):
 148   ldr     R1,=IC_ON
 149   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
 150   orr     R0,R0,R1             @Set I bit
 151   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
 152   bx      LR
 153
 154 ASM_PFX(ArmDisableInstructionCache):
 155   ldr     R1,=IC_ON
 156   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
 157   bic     R0,R0,R1             @Clear I bit.
 158   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
 159   bx      LR
 160
 161 ASM_PFX(ArmEnableBranchPrediction):
 162   mrc     p15, 0, r0, c1, c0, 0
 163   orr     r0, r0, #0x00000800
 164   mcr     p15, 0, r0, c1, c0, 0
 165   bx      LR
 166
 167 ASM_PFX(ArmDisableBranchPrediction):
 168   mrc     p15, 0, r0, c1, c0, 0
 169   bic     r0, r0, #0x00000800
 170   mcr     p15, 0, r0, c1, c0, 0
 171   bx      LR
 172
 173 ASM_PFX(ArmDataMemoryBarrier):
 174   mov R0, #0
 175   mcr P15, #0, R0, C7, C10, #5
 176   bx      LR
 177
 178 ASM_PFX(ArmDataSyncronizationBarrier):
 179   mov R0, #0
 180   mcr P15, #0, R0, C7, C10, #4
 181   bx      LR
 182
 183 ASM_PFX(ArmInstructionSynchronizationBarrier):
 184   mov R0, #0
 185   mcr P15, #0, R0, C7, C5, #4
 186   bx      LR
 187
 188 ASM_PFX(ArmSetLowVectors):
 189   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 190   bic     r0, r0, #0x00002000   @ clear V bit
 191   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 192   bx      LR
 193
 194 ASM_PFX(ArmSetHighVectors):
 195   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 196   orr     r0, r0, #0x00002000   @ clear V bit
 197   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 198   bx      LR
 199
 200 ASM_PFX(ArmIsMpCore):
 201   push    { r1 }
 202   mrc     p15, 0, r0, c0, c0, 0
 203   # Extract Part Number to check it is an ARM11MP core (0xB02)
 204   LoadConstantToReg (Arm11PartNumberMask, r1)
 205   and     r0, r0, r1
 206   LoadConstantToReg (Arm11PartNumber, r1)
 207   cmp     r0, r1
 208   movne   r0, #0
 209   pop     { r1 }
 210   bx      lr
 211
 212 ASM_PFX(ArmCallWFI):
 213   wfi
 214   bx      lr
 215
 216 ASM_PFX(ArmReadMpidr):
 217   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 218   bx      lr
 219
 220 ASM_PFX(ArmReadMpidr):
 221   mrc     p15, 0, r0, c0, c0, 0       @ Read Main ID Register
 222   bx      lr
 223
 224 ASM_PFX(ArmEnableFiq):
 225   mrs     R0,CPSR
 226   bic     R0,R0,#0x40    @Enable FIQ interrupts
 227   msr     CPSR_c,R0
 228   bx      LR
 229
 230 ASM_PFX(ArmDisableFiq):
 231   mrs     R0,CPSR
 232   orr     R1,R0,#0x40    @Disable FIQ interrupts
 233   msr     CPSR_c,R1
 234   tst     R0,#0x80
 235   moveq   R0,#1
 236   movne   R0,#0
 237   bx      LR
 238
 239 ASM_PFX(ArmEnableInterrupts):
 240   mrs     R0,CPSR
 241   bic     R0,R0,#0x80    @Enable IRQ interrupts
 242   msr     CPSR_c,R0
 243   bx      LR
 244
 245 ASM_PFX(ArmDisableInterrupts):
 246   mrs     R0,CPSR
 247   orr     R1,R0,#0x80    @Disable IRQ interrupts
 248   msr     CPSR_c,R1
 249   tst     R0,#0x80
 250   moveq   R0,#1
 251   movne   R0,#0
 252   bx      LR
 253
 254 ASM_PFX(ArmEnableVFP):
 255   # Read CPACR (Coprocessor Access Control Register)
 256   mrc     p15, 0, r0, c1, c0, 2
 257   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 258   orr     r0, r0, #0x00f00000
 259   # Write back CPACR (Coprocessor Access Control Register)
 260   mcr     p15, 0, r0, c1, c0, 2
 261   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 262   mov     r0, #0x40000000
 263   #TODO: Fixme - need compilation flag
 264   #fmxr    FPEXC, r0
 265   bx      lr
 266
 267 ASM_FUNCTION_REMOVE_IF_UNREFERENCED