1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmCleanInvalidateDataCache
16 EXPORT ArmCleanDataCache
17 EXPORT ArmInvalidateDataCache
18 EXPORT ArmInvalidateInstructionCache
19 EXPORT ArmInvalidateDataCacheEntryByMVA
20 EXPORT ArmCleanDataCacheEntryByMVA
21 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
24 EXPORT ArmEnableDataCache
25 EXPORT ArmDisableDataCache
26 EXPORT ArmEnableInstructionCache
27 EXPORT ArmDisableInstructionCache
28 EXPORT ArmEnableBranchPrediction
29 EXPORT ArmDisableBranchPrediction
32 DC_ON EQU ( 0x1:SHL:2 )
33 IC_ON EQU ( 0x1:SHL:12 )
34 XP_ON EQU ( 0x1:SHL:23 )
37 AREA ArmCacheLib, CODE, READONLY
41 ArmInvalidateDataCacheEntryByMVA
42 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
46 ArmCleanDataCacheEntryByMVA
47 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
51 ArmCleanInvalidateDataCacheEntryByMVA
52 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
57 mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
61 ArmCleanInvalidateDataCache
62 mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
66 ArmInvalidateDataCache
67 mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
71 ArmInvalidateInstructionCache
72 mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
74 mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
88 mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
90 mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
95 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
96 ORR R0,R0,R1 ;Set C bit
97 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
102 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
103 BIC R0,R0,R1 ;Clear C bit
104 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
107 ArmEnableInstructionCache
109 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
110 ORR R0,R0,R1 ;Set I bit
111 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
114 ArmDisableInstructionCache
116 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
117 BIC R0,R0,R1 ;Clear I bit.
118 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
121 ArmEnableBranchPrediction
122 mrc p15, 0, r0, c1, c0, 0
123 orr r0, r0, #0x00000800
124 mcr p15, 0, r0, c1, c0, 0
127 ArmDisableBranchPrediction
128 mrc p15, 0, r0, c1, c0, 0
129 bic r0, r0, #0x00000800
130 mcr p15, 0, r0, c1, c0, 0