1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmCleanInvalidateDataCache
16 EXPORT ArmCleanDataCache
17 EXPORT ArmInvalidateDataCache
18 EXPORT ArmInvalidateInstructionCache
19 EXPORT ArmInvalidateDataCacheEntryByMVA
20 EXPORT ArmCleanDataCacheEntryByMVA
21 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
25 EXPORT ArmEnableDataCache
26 EXPORT ArmDisableDataCache
27 EXPORT ArmEnableInstructionCache
28 EXPORT ArmDisableInstructionCache
29 EXPORT ArmEnableBranchPrediction
30 EXPORT ArmDisableBranchPrediction
33 DC_ON EQU ( 0x1:SHL:2 )
34 IC_ON EQU ( 0x1:SHL:12 )
36 AREA ArmCacheLib, CODE, READONLY
40 ArmInvalidateDataCacheEntryByMVA
41 MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
45 ArmCleanDataCacheEntryByMVA
46 MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
50 ArmCleanInvalidateDataCacheEntryByMVA
51 MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
54 ArmEnableInstructionCache
56 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
57 ORR R0,R0,R1 ;Set I bit
58 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
61 ArmDisableInstructionCache
63 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
64 BIC R0,R0,R1 ;Clear I bit.
65 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
68 ArmInvalidateInstructionCache
70 MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
72 MCR p15,0,R0,c7,c10,4 ;Drain write buffer
91 mcr p15,0,R0,c7,c10,4 ;Drain write buffer
96 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
97 ORR R0,R0,R1 ;Set C bit
98 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
103 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
104 BIC R0,R0,R1 ;Clear C bit
105 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
109 MRC p15,0,r15,c7,c10,3
110 BNE ArmCleanDataCache
112 MCR p15,0,R0,c7,c10,4 ;Drain write buffer
115 ArmInvalidateDataCache
117 MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
119 MCR p15,0,R0,c7,c10,4 ;Drain write buffer
122 ArmCleanInvalidateDataCache
123 MRC p15,0,r15,c7,c14,3
124 BNE ArmCleanInvalidateDataCache
126 MCR p15,0,R0,c7,c10,4 ;Drain write buffer
129 ArmEnableBranchPrediction
130 bx LR ;Branch prediction is not supported.
132 ArmDisableBranchPrediction
133 bx LR ;Branch prediction is not supported.