1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
5 # This program and the accompanying materials
6 # are licensed and made available under the terms and conditions of the BSD License
7 # which accompanies this distribution. The full text of the license may be found at
8 # http://opensource.org/licenses/bsd-license.php
10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #------------------------------------------------------------------------------
15 #include <AsmMacroIoLib.h>
20 GCC_ASM_EXPORT(Cp15IdCode)
21 GCC_ASM_EXPORT(Cp15CacheInfo)
22 GCC_ASM_EXPORT(ArmIsMPCore)
23 GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
24 GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
25 GCC_ASM_EXPORT(ArmEnableIrq)
26 GCC_ASM_EXPORT(ArmDisableIrq)
27 GCC_ASM_EXPORT(ArmGetInterruptState)
28 GCC_ASM_EXPORT(ArmEnableFiq)
29 GCC_ASM_EXPORT(ArmDisableFiq)
30 GCC_ASM_EXPORT(ArmEnableInterrupts)
31 GCC_ASM_EXPORT(ArmDisableInterrupts)
32 GCC_ASM_EXPORT(ArmGetFiqState)
33 GCC_ASM_EXPORT(ArmInvalidateTlb)
34 GCC_ASM_EXPORT(ArmSetTTBR0)
35 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
36 GCC_ASM_EXPORT(ArmSetDomainAccessControl)
37 GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
38 GCC_ASM_EXPORT(CPSRMaskInsert)
39 GCC_ASM_EXPORT(CPSRRead)
40 GCC_ASM_EXPORT(ReadCCSIDR)
41 GCC_ASM_EXPORT(ReadCLIDR)
45 #------------------------------------------------------------------------------
51 ASM_PFX(Cp15CacheInfo):
57 // Get Multiprocessing extension (bit31) & U bit (bit30)
58 and R0, R0, #0xC0000000
59 // if bit30 == 0 then the processor is part of a multiprocessor system)
60 and R0, R0, #0x80000000
63 ASM_PFX(ArmEnableAsynchronousAbort):
68 ASM_PFX(ArmDisableAsynchronousAbort):
73 ASM_PFX(ArmEnableIrq):
78 ASM_PFX(ArmDisableIrq):
83 ASM_PFX(ArmGetInterruptState):
85 tst R0,#0x80 @Check if IRQ is enabled.
90 ASM_PFX(ArmEnableFiq):
95 ASM_PFX(ArmDisableFiq):
100 ASM_PFX(ArmEnableInterrupts):
105 ASM_PFX(ArmDisableInterrupts):
110 ASM_PFX(ArmGetFiqState):
112 tst R0,#0x40 @Check if FIQ is enabled.
117 ASM_PFX(ArmInvalidateTlb):
120 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
125 ASM_PFX(ArmSetTTBR0):
130 ASM_PFX(ArmGetTTBR0BaseAddress):
132 LoadConstantToReg(0xFFFFC000, r1)
138 ASM_PFX(ArmSetDomainAccessControl):
145 //ArmUpdateTranslationTableEntry (
146 // IN VOID *TranslationTableEntry // R0
147 // IN VOID *MVA // R1
149 ASM_PFX(ArmUpdateTranslationTableEntry):
150 mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
152 mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
153 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
158 ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
159 stmfd sp!, {r4-r12, lr} @ save all the banked registers
160 mov r3, sp @ copy the stack pointer into a non-banked register
161 mrs r2, cpsr @ read the cpsr
162 bic r2, r2, r0 @ clear mask in the cpsr
163 and r1, r1, r0 @ clear bits outside the mask in the input
164 orr r2, r2, r1 @ set field
165 msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
167 mov sp, r3 @ restore stack pointer
168 ldmfd sp!, {r4-r12, lr} @ restore registers
169 bx lr @ return (hopefully thumb-safe!)
180 mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
182 mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
190 mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
193 ASM_FUNCTION_REMOVE_IF_UNREFERENCED