1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
18 EXPORT ArmEnableInterrupts
19 EXPORT ArmDisableInterrupts
20 EXPORT ArmGetInterruptState
21 EXPORT ArmInvalidateTlb
22 EXPORT ArmSetTranslationTableBaseAddress
23 EXPORT ArmGetTranslationTableBaseAddress
24 EXPORT ArmSetDomainAccessControl
30 AREA ArmLibSupport, CODE, READONLY
50 tst R0,#0x80 ;Check if IRQ is enabled.
61 ArmSetTranslationTableBaseAddress
66 ArmGetTranslationTableBaseAddress
71 ArmSetDomainAccessControl
76 CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
77 stmfd sp!, {r4-r12, lr} ; save all the banked registers
78 mov r3, sp ; copy the stack pointer into a non-banked register
79 mrs r2, cpsr ; read the cpsr
80 bic r2, r2, r0 ; clear mask in the cpsr
81 and r1, r1, r0 ; clear bits outside the mask in the input
82 orr r2, r2, r1 ; set field
83 msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
85 mov sp, r3 ; restore stack pointer
86 ldmfd sp!, {r4-r12, lr} ; restore registers
87 bx lr ; return (hopefully thumb-safe!)
99 MCR p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
101 MRC p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
110 MRC p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register