ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16
  17     EXPORT  ArmIsMpCore
  18     EXPORT  ArmEnableAsynchronousAbort
  19     EXPORT  ArmDisableAsynchronousAbort
  20     EXPORT  ArmEnableIrq
  21     EXPORT  ArmDisableIrq
  22     EXPORT  ArmEnableFiq
  23     EXPORT  ArmDisableFiq
  24     EXPORT  ArmEnableInterrupts
  25     EXPORT  ArmDisableInterrupts
  26     EXPORT  ReadCCSIDR
  27     EXPORT  ReadCLIDR
  28     EXPORT  ArmReadNsacr
  29     EXPORT  ArmWriteNsacr
  30
  31     AREA ArmLibSupportV7, CODE, READONLY
  32
  33
  34 //------------------------------------------------------------------------------
  35
  36 ArmIsMpCore
  37   mrc     p15,0,R0,c0,c0,5
  38   // Get Multiprocessing extension (bit31) & U bit (bit30)
  39   and     R0, R0, #0xC0000000
  40   // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
  41   cmp     R0, #0x80000000
  42   moveq   R0, #1
  43   movne   R0, #0
  44   bx      LR
  45
  46 ArmEnableAsynchronousAbort
  47   cpsie   a
  48   isb
  49   bx      LR
  50
  51 ArmDisableAsynchronousAbort
  52   cpsid   a
  53   isb
  54   bx      LR
  55
  56 ArmEnableIrq
  57   cpsie   i
  58   isb
  59   bx      LR
  60
  61 ArmDisableIrq
  62   cpsid   i
  63   isb
  64   bx      LR
  65
  66 ArmEnableFiq
  67   cpsie   f
  68   isb
  69   bx      LR
  70
  71 ArmDisableFiq
  72   cpsid   f
  73   isb
  74   bx      LR
  75
  76 ArmEnableInterrupts
  77   cpsie   if
  78   isb
  79   bx      LR
  80
  81 ArmDisableInterrupts
  82   cpsid   if
  83   isb
  84   bx      LR
  85
  86 // UINT32
  87 // ReadCCSIDR (
  88 //   IN UINT32 CSSELR
  89 //   )
  90 ReadCCSIDR
  91   mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
  92   isb
  93   mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
  94   bx  lr
  95
  96 // UINT32
  97 // ReadCLIDR (
  98 //   IN UINT32 CSSELR
  99 //   )
 100 ReadCLIDR
 101   mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
 102   bx  lr
 103
 104 ArmReadNsacr
 105   mrc     p15, 0, r0, c1, c1, 2
 106   bx      lr
 107
 108 ArmWriteNsacr
 109   mcr     p15, 0, r0, c1, c1, 2
 110   bx      lr
 111
 112   END