1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
5 # This program and the accompanying materials
6 # are licensed and made available under the terms and conditions of the BSD License
7 # which accompanies this distribution. The full text of the license may be found at
8 # http://opensource.org/licenses/bsd-license.php
10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #------------------------------------------------------------------------------
18 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
19 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
20 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
21 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
22 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
23 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
24 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
25 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
26 GCC_ASM_EXPORT (ArmEnableMmu)
27 GCC_ASM_EXPORT (ArmDisableMmu)
28 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
29 GCC_ASM_EXPORT (ArmMmuEnabled)
30 GCC_ASM_EXPORT (ArmEnableDataCache)
31 GCC_ASM_EXPORT (ArmDisableDataCache)
32 GCC_ASM_EXPORT (ArmEnableInstructionCache)
33 GCC_ASM_EXPORT (ArmDisableInstructionCache)
34 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
35 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
36 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
37 GCC_ASM_EXPORT (ArmSetLowVectors)
38 GCC_ASM_EXPORT (ArmSetHighVectors)
39 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
40 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
41 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
42 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
43 GCC_ASM_EXPORT (ArmWriteNsacr)
44 GCC_ASM_EXPORT (ArmWriteScr)
45 GCC_ASM_EXPORT (ArmWriteVMBar)
46 GCC_ASM_EXPORT (ArmWriteVBar)
47 GCC_ASM_EXPORT (ArmWriteCPACR)
48 GCC_ASM_EXPORT (ArmEnableVFP)
49 GCC_ASM_EXPORT (ArmCallWFI)
50 GCC_ASM_EXPORT (ArmWriteAuxCr)
51 GCC_ASM_EXPORT (ArmReadAuxCr)
52 GCC_ASM_EXPORT (ArmReadCbar)
53 GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
54 GCC_ASM_EXPORT (ArmReadMpidr)
55 GCC_ASM_EXPORT (ArmReadTpidrurw)
56 GCC_ASM_EXPORT (ArmWriteTpidrurw)
60 .set CTRL_M_BIT, (1 << 0)
61 .set CTRL_C_BIT, (1 << 2)
62 .set CTRL_B_BIT, (1 << 7)
63 .set CTRL_I_BIT, (1 << 12)
66 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
67 mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
72 ASM_PFX(ArmCleanDataCacheEntryByMVA):
73 mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
79 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
80 mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
86 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
87 mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
93 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
94 mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
100 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
101 mcr p15, 0, r0, c7, c10, 2 @ Clean this line
106 ASM_PFX(ArmInvalidateInstructionCache):
107 mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
112 ASM_PFX(ArmEnableMmu):
121 ASM_PFX(ArmDisableMmu):
124 mcr p15,0,R0,c1,c0,0 @Disable MMU
126 mcr p15,0,R0,c8,c7,0 @Invalidate TLB
127 mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
132 ASM_PFX(ArmDisableCachesAndMmu):
133 mrc p15, 0, r0, c1, c0, 0 @ Get control register
134 bic r0, r0, #CTRL_M_BIT @ Disable MMU
135 bic r0, r0, #CTRL_C_BIT @ Disable D Cache
136 bic r0, r0, #CTRL_I_BIT @ Disable I Cache
137 mcr p15, 0, r0, c1, c0, 0 @ Write control register
142 ASM_PFX(ArmMmuEnabled):
147 ASM_PFX(ArmEnableDataCache):
149 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
150 orr R0,R0,R1 @Set C bit
151 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
156 ASM_PFX(ArmDisableDataCache):
158 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
159 bic R0,R0,R1 @Clear C bit
160 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
165 ASM_PFX(ArmEnableInstructionCache):
167 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
168 orr R0,R0,R1 @Set I bit
169 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
174 ASM_PFX(ArmDisableInstructionCache):
176 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
177 bic R0,R0,R1 @Clear I bit.
178 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
183 ASM_PFX(ArmEnableSWPInstruction):
184 mrc p15, 0, r0, c1, c0, 0
185 orr r0, r0, #0x00000400
186 mcr p15, 0, r0, c1, c0, 0
190 ASM_PFX(ArmEnableBranchPrediction):
191 mrc p15, 0, r0, c1, c0, 0
192 orr r0, r0, #0x00000800
193 mcr p15, 0, r0, c1, c0, 0
198 ASM_PFX(ArmDisableBranchPrediction):
199 mrc p15, 0, r0, c1, c0, 0
200 bic r0, r0, #0x00000800
201 mcr p15, 0, r0, c1, c0, 0
206 ASM_PFX(ArmSetLowVectors):
207 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
208 bic r0, r0, #0x00002000 @ clear V bit
209 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
213 ASM_PFX(ArmSetHighVectors):
214 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
215 orr r0, r0, #0x00002000 @ clear V bit
216 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
220 ASM_PFX(ArmV7AllDataCachesOperation):
221 stmfd SP!,{r4-r12, LR}
222 mov R1, R0 @ Save Function call in R1
223 mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
224 ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
225 mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
230 add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
231 mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
232 and R12, R12, #7 @ get those 3 bits alone
234 blt L_Skip @ no cache or only instruction cache at this level
235 mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
236 isb @ isb to sync the change to the CacheSizeID reg
237 mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
238 and R2, R12, #0x7 @ extract the line length field
239 add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
243 ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
244 clz R5, R4 @ R5 is the bit position of the way size increment
245 @ ldr R7, =0x00007FFF
248 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
251 mov R9, R4 @ R9 working copy of the max way size (right aligned)
254 orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
255 orr R0, R0, R7, LSL R2 @ factor in the index number
259 subs R9, R9, #1 @ decrement the way number
261 subs R7, R7, #1 @ decrement the index
264 add R10, R10, #2 @ increment the cache number
270 ldmfd SP!, {r4-r12, lr}
273 ASM_PFX(ArmDataMemoryBarrier):
277 ASM_PFX(ArmDataSyncronizationBarrier):
278 ASM_PFX(ArmDrainWriteBuffer):
282 ASM_PFX(ArmInstructionSynchronizationBarrier):
286 ASM_PFX(ArmWriteNsacr):
287 mcr p15, 0, r0, c1, c1, 2
290 ASM_PFX(ArmWriteScr):
291 mcr p15, 0, r0, c1, c1, 0
294 ASM_PFX(ArmWriteAuxCr):
295 mcr p15, 0, r0, c1, c0, 1
298 ASM_PFX(ArmReadAuxCr):
299 mrc p15, 0, r0, c1, c0, 1
302 ASM_PFX(ArmWriteVMBar):
303 mcr p15, 0, r0, c12, c0, 1
306 ASM_PFX(ArmWriteVBar):
307 # Set the Address of the Vector Table in the VBAR register
308 mcr p15, 0, r0, c12, c0, 0
309 # Ensure the SCTLR.V bit is clear
310 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
311 bic r0, r0, #0x00002000 @ clear V bit
312 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
316 ASM_PFX(ArmWriteCPACR):
317 mcr p15, 0, r0, c1, c0, 2
320 ASM_PFX(ArmEnableVFP):
321 # Read CPACR (Coprocessor Access Control Register)
322 mrc p15, 0, r0, c1, c0, 2
323 # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
324 orr r0, r0, #0x00f00000
325 # Write back CPACR (Coprocessor Access Control Register)
326 mcr p15, 0, r0, c1, c0, 2
327 # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
329 mcr p10,#0x7,r0,c8,c0,#0
336 #Note: Return 0 in Uniprocessor implementation
337 ASM_PFX(ArmReadCbar):
338 mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
341 ASM_PFX(ArmInvalidateInstructionAndDataTlb):
342 mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
346 ASM_PFX(ArmReadMpidr):
347 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
350 ASM_PFX(ArmReadTpidrurw):
351 mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
354 ASM_PFX(ArmWriteTpidrurw):
355 mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
358 ASM_FUNCTION_REMOVE_IF_UNREFERENCED