1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4 # Copyright (c) 2011, ARM Limited. All rights reserved.
6 # This program and the accompanying materials
7 # are licensed and made available under the terms and conditions of the BSD License
8 # which accompanies this distribution. The full text of the license may be found at
9 # http://opensource.org/licenses/bsd-license.php
11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #------------------------------------------------------------------------------
19 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
20 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
21 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
22 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
26 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
27 GCC_ASM_EXPORT (ArmEnableMmu)
28 GCC_ASM_EXPORT (ArmDisableMmu)
29 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
30 GCC_ASM_EXPORT (ArmMmuEnabled)
31 GCC_ASM_EXPORT (ArmEnableDataCache)
32 GCC_ASM_EXPORT (ArmDisableDataCache)
33 GCC_ASM_EXPORT (ArmEnableInstructionCache)
34 GCC_ASM_EXPORT (ArmDisableInstructionCache)
35 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
36 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
37 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
38 GCC_ASM_EXPORT (ArmSetLowVectors)
39 GCC_ASM_EXPORT (ArmSetHighVectors)
40 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
41 GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)
42 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
43 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
44 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
45 GCC_ASM_EXPORT (ArmWriteVBar)
46 GCC_ASM_EXPORT (ArmEnableVFP)
47 GCC_ASM_EXPORT (ArmCallWFI)
48 GCC_ASM_EXPORT (ArmReadCbar)
49 GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
50 GCC_ASM_EXPORT (ArmReadMpidr)
51 GCC_ASM_EXPORT (ArmReadTpidrurw)
52 GCC_ASM_EXPORT (ArmWriteTpidrurw)
53 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
54 GCC_ASM_EXPORT (ArmReadIdPfr1)
58 .set CTRL_M_BIT, (1 << 0)
59 .set CTRL_C_BIT, (1 << 2)
60 .set CTRL_B_BIT, (1 << 7)
61 .set CTRL_I_BIT, (1 << 12)
64 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
65 mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
70 ASM_PFX(ArmCleanDataCacheEntryByMVA):
71 mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
77 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
78 mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
84 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
85 mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
91 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
92 mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
98 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
99 mcr p15, 0, r0, c7, c10, 2 @ Clean this line
104 ASM_PFX(ArmInvalidateInstructionCache):
105 mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
110 ASM_PFX(ArmEnableMmu):
119 ASM_PFX(ArmDisableMmu):
122 mcr p15,0,R0,c1,c0,0 @Disable MMU
124 mcr p15,0,R0,c8,c7,0 @Invalidate TLB
125 mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
130 ASM_PFX(ArmDisableCachesAndMmu):
131 mrc p15, 0, r0, c1, c0, 0 @ Get control register
132 bic r0, r0, #CTRL_M_BIT @ Disable MMU
133 bic r0, r0, #CTRL_C_BIT @ Disable D Cache
134 bic r0, r0, #CTRL_I_BIT @ Disable I Cache
135 mcr p15, 0, r0, c1, c0, 0 @ Write control register
140 ASM_PFX(ArmMmuEnabled):
145 ASM_PFX(ArmEnableDataCache):
147 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
148 orr R0,R0,R1 @Set C bit
149 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
154 ASM_PFX(ArmDisableDataCache):
156 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
157 bic R0,R0,R1 @Clear C bit
158 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
163 ASM_PFX(ArmEnableInstructionCache):
165 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
166 orr R0,R0,R1 @Set I bit
167 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
172 ASM_PFX(ArmDisableInstructionCache):
174 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
175 bic R0,R0,R1 @Clear I bit.
176 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
181 ASM_PFX(ArmEnableSWPInstruction):
182 mrc p15, 0, r0, c1, c0, 0
183 orr r0, r0, #0x00000400
184 mcr p15, 0, r0, c1, c0, 0
188 ASM_PFX(ArmEnableBranchPrediction):
189 mrc p15, 0, r0, c1, c0, 0
190 orr r0, r0, #0x00000800
191 mcr p15, 0, r0, c1, c0, 0
196 ASM_PFX(ArmDisableBranchPrediction):
197 mrc p15, 0, r0, c1, c0, 0
198 bic r0, r0, #0x00000800
199 mcr p15, 0, r0, c1, c0, 0
204 ASM_PFX(ArmSetLowVectors):
205 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
206 bic r0, r0, #0x00002000 @ clear V bit
207 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
211 ASM_PFX(ArmSetHighVectors):
212 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
213 orr r0, r0, #0x00002000 @ clear V bit
214 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
218 ASM_PFX(ArmV7AllDataCachesOperation):
219 stmfd SP!,{r4-r12, LR}
220 mov R1, R0 @ Save Function call in R1
221 mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
222 ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
223 mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
228 add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
229 mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
230 and R12, R12, #7 @ get those 3 bits alone
232 blt L_Skip @ no cache or only instruction cache at this level
233 mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
234 isb @ isb to sync the change to the CacheSizeID reg
235 mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
236 and R2, R12, #0x7 @ extract the line length field
237 add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
241 ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
242 clz R5, R4 @ R5 is the bit position of the way size increment
243 @ ldr R7, =0x00007FFF
246 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
249 mov R9, R4 @ R9 working copy of the max way size (right aligned)
252 orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
253 orr R0, R0, R7, LSL R2 @ factor in the index number
257 subs R9, R9, #1 @ decrement the way number
259 subs R7, R7, #1 @ decrement the index
262 add R10, R10, #2 @ increment the cache number
268 ldmfd SP!, {r4-r12, lr}
271 ASM_PFX(ArmV7PerformPoUDataCacheOperation):
272 stmfd SP!,{r4-r12, LR}
273 mov R1, R0 @ Save Function call in R1
274 mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
275 ands R3, R6, #0x38000000 @ Mask out all but Level of Unification (LoU)
276 mov R3, R3, LSR #26 @ Cache level value (naturally aligned)
281 add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
282 mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
283 and R12, R12, #7 @ get those 3 bits alone
285 blt Skip2 @ no cache or only instruction cache at this level
286 mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
287 isb @ isb to sync the change to the CacheSizeID reg
288 mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
289 and R2, R12, #0x7 @ extract the line length field
290 add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
292 ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
293 clz R5, R4 @ R5 is the bit position of the way size increment
295 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
298 mov R9, R4 @ R9 working copy of the max way size (right aligned)
301 orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
302 orr R0, R0, R7, LSL R2 @ factor in the index number
306 subs R9, R9, #1 @ decrement the way number
308 subs R7, R7, #1 @ decrement the index
311 add R10, R10, #2 @ increment the cache number
317 ldmfd SP!, {r4-r12, lr}
320 ASM_PFX(ArmDataMemoryBarrier):
324 ASM_PFX(ArmDataSyncronizationBarrier):
325 ASM_PFX(ArmDrainWriteBuffer):
329 ASM_PFX(ArmInstructionSynchronizationBarrier):
333 ASM_PFX(ArmWriteVBar):
334 # Set the Address of the Vector Table in the VBAR register
335 mcr p15, 0, r0, c12, c0, 0
336 # Ensure the SCTLR.V bit is clear
337 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
338 bic r0, r0, #0x00002000 @ clear V bit
339 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
343 ASM_PFX(ArmEnableVFP):
344 # Read CPACR (Coprocessor Access Control Register)
345 mrc p15, 0, r0, c1, c0, 2
346 # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
347 orr r0, r0, #0x00f00000
348 # Write back CPACR (Coprocessor Access Control Register)
349 mcr p15, 0, r0, c1, c0, 2
350 # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
352 mcr p10,#0x7,r0,c8,c0,#0
359 #Note: Return 0 in Uniprocessor implementation
360 ASM_PFX(ArmReadCbar):
361 mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
364 ASM_PFX(ArmInvalidateInstructionAndDataTlb):
365 mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB
369 ASM_PFX(ArmReadMpidr):
370 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
373 ASM_PFX(ArmReadTpidrurw):
374 mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
377 ASM_PFX(ArmWriteTpidrurw):
378 mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
381 ASM_PFX(ArmIsArchTimerImplemented):
382 mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1
383 and r0, r0, #0x000F0000
386 ASM_PFX(ArmReadIdPfr1):
387 mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register
390 ASM_FUNCTION_REMOVE_IF_UNREFERENCED