1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
6 # This program and the accompanying materials
7 # are licensed and made available under the terms and conditions of the BSD License
8 # which accompanies this distribution. The full text of the license may be found at
9 # http://opensource.org/licenses/bsd-license.php
11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #------------------------------------------------------------------------------
16 #include <AsmMacroIoLib.h>
19 // No memory barriers for ARMv6
26 GCC_ASM_EXPORT(ArmReadMidr)
27 GCC_ASM_EXPORT(Cp15CacheInfo)
28 GCC_ASM_EXPORT(ArmGetInterruptState)
29 GCC_ASM_EXPORT(ArmGetFiqState)
30 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
31 GCC_ASM_EXPORT(ArmSetTTBR0)
32 GCC_ASM_EXPORT(ArmSetDomainAccessControl)
33 GCC_ASM_EXPORT(CPSRMaskInsert)
34 GCC_ASM_EXPORT(CPSRRead)
35 GCC_ASM_EXPORT(ArmReadCpacr)
36 GCC_ASM_EXPORT(ArmWriteCpacr)
37 GCC_ASM_EXPORT(ArmWriteAuxCr)
38 GCC_ASM_EXPORT(ArmReadAuxCr)
39 GCC_ASM_EXPORT(ArmInvalidateTlb)
40 GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
41 GCC_ASM_EXPORT(ArmReadScr)
42 GCC_ASM_EXPORT(ArmWriteScr)
43 GCC_ASM_EXPORT(ArmReadMVBar)
44 GCC_ASM_EXPORT(ArmWriteMVBar)
45 GCC_ASM_EXPORT(ArmReadHVBar)
46 GCC_ASM_EXPORT(ArmWriteHVBar)
47 GCC_ASM_EXPORT(ArmCallWFE)
48 GCC_ASM_EXPORT(ArmCallSEV)
49 GCC_ASM_EXPORT(ArmReadSctlr)
51 #------------------------------------------------------------------------------
57 ASM_PFX(Cp15CacheInfo):
61 ASM_PFX(ArmGetInterruptState):
63 tst R0,#0x80 @Check if IRQ is enabled.
68 ASM_PFX(ArmGetFiqState):
70 tst R0,#0x40 @Check if FIQ is enabled.
75 ASM_PFX(ArmSetDomainAccessControl):
79 ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
80 stmfd sp!, {r4-r12, lr} @ save all the banked registers
81 mov r3, sp @ copy the stack pointer into a non-banked register
82 mrs r2, cpsr @ read the cpsr
83 bic r2, r2, r0 @ clear mask in the cpsr
84 and r1, r1, r0 @ clear bits outside the mask in the input
85 orr r2, r2, r1 @ set field
86 msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
88 mov sp, r3 @ restore stack pointer
89 ldmfd sp!, {r4-r12, lr} @ restore registers
90 bx lr @ return (hopefully thumb-safe!) @ return (hopefully thumb-safe!)
96 ASM_PFX(ArmReadCpacr):
97 mrc p15, 0, r0, c1, c0, 2
100 ASM_PFX(ArmWriteCpacr):
101 mcr p15, 0, r0, c1, c0, 2
105 ASM_PFX(ArmWriteAuxCr):
106 mcr p15, 0, r0, c1, c0, 1
109 ASM_PFX(ArmReadAuxCr):
110 mrc p15, 0, r0, c1, c0, 1
113 ASM_PFX(ArmSetTTBR0):
118 ASM_PFX(ArmGetTTBR0BaseAddress):
120 LoadConstantToReg(0xFFFFC000, r1)
127 //ArmUpdateTranslationTableEntry (
128 // IN VOID *TranslationTableEntry // R0
129 // IN VOID *MVA // R1
131 ASM_PFX(ArmUpdateTranslationTableEntry):
132 mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
134 mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
135 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
140 ASM_PFX(ArmInvalidateTlb):
143 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
149 mrc p15, 0, r0, c1, c1, 0
152 ASM_PFX(ArmWriteScr):
153 mcr p15, 0, r0, c1, c1, 0
156 ASM_PFX(ArmReadHVBar):
157 mrc p15, 4, r0, c12, c0, 0
160 ASM_PFX(ArmWriteHVBar):
161 mcr p15, 4, r0, c12, c0, 0
165 ASM_PFX(ArmReadMVBar):
166 mrc p15, 0, r0, c12, c0, 1
169 ASM_PFX(ArmWriteMVBar):
170 mcr p15, 0, r0, c12, c0, 1
181 ASM_PFX(ArmReadSctlr):
182 mrc p15, 0, R0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
185 ASM_FUNCTION_REMOVE_IF_UNREFERENCED