2 * File managing the MMU for ARMv8 architecture
4 * Copyright (c) 2011-2020, ARM Limited. All rights reserved.
5 * Copyright (c) 2016, Linaro Limited. All rights reserved.
6 * Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
8 * SPDX-License-Identifier: BSD-2-Clause-Patent
13 #include <Chipset/AArch64.h>
14 #include <Library/BaseMemoryLib.h>
15 #include <Library/CacheMaintenanceLib.h>
16 #include <Library/MemoryAllocationLib.h>
17 #include <Library/ArmLib.h>
18 #include <Library/ArmMmuLib.h>
19 #include <Library/BaseLib.h>
20 #include <Library/DebugLib.h>
21 #include <Library/HobLib.h>
25 EFIAPI
*mReplaceLiveEntryFunc
29 IN UINT64 RegionStart
,
31 ) = ArmReplaceLiveTranslationEntry
;
35 ArmMemoryAttributeToPageAttribute (
36 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
40 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE
:
41 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE
:
42 return TT_ATTR_INDX_MEMORY_WRITE_BACK
;
44 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
:
45 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
:
46 return TT_ATTR_INDX_MEMORY_WRITE_BACK
| TT_SH_INNER_SHAREABLE
;
48 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
:
49 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
:
50 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH
| TT_SH_INNER_SHAREABLE
;
52 // Uncached and device mappings are treated as outer shareable by default,
53 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
:
54 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
:
55 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE
;
59 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
:
60 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
:
61 if (ArmReadCurrentEL () == AARCH64_EL2
) {
62 return TT_ATTR_INDX_DEVICE_MEMORY
| TT_XN_MASK
;
64 return TT_ATTR_INDX_DEVICE_MEMORY
| TT_UXN_MASK
| TT_PXN_MASK
;
70 #define BITS_PER_LEVEL 9
71 #define MAX_VA_BITS 48
75 GetRootTableEntryCount (
79 return TT_ENTRY_COUNT
>> (T0SZ
- MIN_T0SZ
) % BITS_PER_LEVEL
;
88 return (T0SZ
- MIN_T0SZ
) / BITS_PER_LEVEL
;
96 IN UINT64 RegionStart
,
98 IN BOOLEAN IsLiveBlockMapping
104 // Replacing a live block entry with a table entry (or vice versa) requires a
105 // break-before-make sequence as per the architecture. This means the mapping
106 // must be made invalid and cleaned from the TLBs first, and this is a bit of
107 // a hassle if the mapping in question covers the code that is actually doing
108 // the mapping and the unmapping, and so we only bother with this if actually
112 if (!IsLiveBlockMapping
|| !ArmMmuEnabled ()) {
113 // If the mapping is not a live block mapping, or the MMU is not on yet, we
114 // can simply overwrite the entry.
116 ArmUpdateTranslationTableEntry (Entry
, (VOID
*)(UINTN
)RegionStart
);
118 // If the mapping in question does not cover the code that updates the
119 // entry in memory, or the entry that we are intending to update, we can
120 // use an ordinary break before make. Otherwise, we will need to
121 // temporarily disable the MMU.
123 if ((((RegionStart
^ (UINTN
)ArmReplaceLiveTranslationEntry
) & ~BlockMask
) == 0) ||
124 (((RegionStart
^ (UINTN
)Entry
) & ~BlockMask
) == 0))
127 DEBUG ((DEBUG_WARN
, "%a: splitting block entry with MMU disabled\n", __FUNCTION__
));
130 ArmReplaceLiveTranslationEntry (Entry
, Value
, RegionStart
, DisableMmu
);
136 FreePageTablesRecursive (
137 IN UINT64
*TranslationTable
,
146 for (Index
= 0; Index
< TT_ENTRY_COUNT
; Index
++) {
147 if ((TranslationTable
[Index
] & TT_TYPE_MASK
) == TT_TYPE_TABLE_ENTRY
) {
148 FreePageTablesRecursive (
149 (VOID
*)(UINTN
)(TranslationTable
[Index
] &
150 TT_ADDRESS_MASK_BLOCK_ENTRY
),
157 FreePages (TranslationTable
, 1);
168 return (Entry
& TT_TYPE_MASK
) == TT_TYPE_BLOCK_ENTRY_LEVEL3
;
171 return (Entry
& TT_TYPE_MASK
) == TT_TYPE_BLOCK_ENTRY
;
183 // TT_TYPE_TABLE_ENTRY aliases TT_TYPE_BLOCK_ENTRY_LEVEL3
184 // so we need to take the level into account as well.
189 return (Entry
& TT_TYPE_MASK
) == TT_TYPE_TABLE_ENTRY
;
194 UpdateRegionMappingRecursive (
195 IN UINT64 RegionStart
,
197 IN UINT64 AttributeSetMask
,
198 IN UINT64 AttributeClearMask
,
199 IN UINT64
*PageTable
,
201 IN BOOLEAN TableIsLive
209 VOID
*TranslationTable
;
211 BOOLEAN NextTableIsLive
;
213 ASSERT (((RegionStart
| RegionEnd
) & EFI_PAGE_MASK
) == 0);
215 BlockShift
= (Level
+ 1) * BITS_PER_LEVEL
+ MIN_T0SZ
;
216 BlockMask
= MAX_UINT64
>> BlockShift
;
220 "%a(%d): %llx - %llx set %lx clr %lx\n",
229 for ( ; RegionStart
< RegionEnd
; RegionStart
= BlockEnd
) {
230 BlockEnd
= MIN (RegionEnd
, (RegionStart
| BlockMask
) + 1);
231 Entry
= &PageTable
[(RegionStart
>> (64 - BlockShift
)) & (TT_ENTRY_COUNT
- 1)];
234 // If RegionStart or BlockEnd is not aligned to the block size at this
235 // level, we will have to create a table mapping in order to map less
236 // than a block, and recurse to create the block or page entries at
237 // the next level. No block mappings are allowed at all at level 0,
238 // so in that case, we have to recurse unconditionally.
240 // One special case to take into account is any region that covers the page
241 // table itself: if we'd cover such a region with block mappings, we are
242 // more likely to end up in the situation later where we need to disable
243 // the MMU in order to update page table entries safely, so prefer page
244 // mappings in that particular case.
246 if ((Level
== 0) || (((RegionStart
| BlockEnd
) & BlockMask
) != 0) ||
247 ((Level
< 3) && (((UINT64
)PageTable
& ~BlockMask
) == RegionStart
)) ||
248 IsTableEntry (*Entry
, Level
))
252 if (!IsTableEntry (*Entry
, Level
)) {
254 // No table entry exists yet, so we need to allocate a page table
255 // for the next level.
257 TranslationTable
= AllocatePages (1);
258 if (TranslationTable
== NULL
) {
259 return EFI_OUT_OF_RESOURCES
;
262 if (!ArmMmuEnabled ()) {
264 // Make sure we are not inadvertently hitting in the caches
265 // when populating the page tables.
267 InvalidateDataCacheRange (TranslationTable
, EFI_PAGE_SIZE
);
270 ZeroMem (TranslationTable
, EFI_PAGE_SIZE
);
272 if (IsBlockEntry (*Entry
, Level
)) {
274 // We are splitting an existing block entry, so we have to populate
275 // the new table with the attributes of the block entry it replaces.
277 Status
= UpdateRegionMappingRecursive (
278 RegionStart
& ~BlockMask
,
279 (RegionStart
| BlockMask
) + 1,
280 *Entry
& TT_ATTRIBUTES_MASK
,
286 if (EFI_ERROR (Status
)) {
288 // The range we passed to UpdateRegionMappingRecursive () is block
289 // aligned, so it is guaranteed that no further pages were allocated
290 // by it, and so we only have to free the page we allocated here.
292 FreePages (TranslationTable
, 1);
297 NextTableIsLive
= FALSE
;
299 TranslationTable
= (VOID
*)(UINTN
)(*Entry
& TT_ADDRESS_MASK_BLOCK_ENTRY
);
300 NextTableIsLive
= TableIsLive
;
304 // Recurse to the next level
306 Status
= UpdateRegionMappingRecursive (
315 if (EFI_ERROR (Status
)) {
316 if (!IsTableEntry (*Entry
, Level
)) {
318 // We are creating a new table entry, so on failure, we can free all
319 // allocations we made recursively, given that the whole subhierarchy
320 // has not been wired into the live page tables yet. (This is not
321 // possible for existing table entries, since we cannot revert the
322 // modifications we made to the subhierarchy it represents.)
324 FreePageTablesRecursive (TranslationTable
, Level
+ 1);
330 if (!IsTableEntry (*Entry
, Level
)) {
331 EntryValue
= (UINTN
)TranslationTable
| TT_TYPE_TABLE_ENTRY
;
337 TableIsLive
&& IsBlockEntry (*Entry
, Level
)
341 EntryValue
= (*Entry
& AttributeClearMask
) | AttributeSetMask
;
342 EntryValue
|= RegionStart
;
343 EntryValue
|= (Level
== 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3
344 : TT_TYPE_BLOCK_ENTRY
;
346 ReplaceTableEntry (Entry
, EntryValue
, RegionStart
, BlockMask
, FALSE
);
355 UpdateRegionMapping (
356 IN UINT64 RegionStart
,
357 IN UINT64 RegionLength
,
358 IN UINT64 AttributeSetMask
,
359 IN UINT64 AttributeClearMask
,
360 IN UINT64
*RootTable
,
361 IN BOOLEAN TableIsLive
366 if (((RegionStart
| RegionLength
) & EFI_PAGE_MASK
) != 0) {
367 return EFI_INVALID_PARAMETER
;
370 T0SZ
= ArmGetTCR () & TCR_T0SZ_MASK
;
372 return UpdateRegionMappingRecursive (
374 RegionStart
+ RegionLength
,
378 GetRootTableLevel (T0SZ
),
385 FillTranslationTable (
386 IN UINT64
*RootTable
,
387 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryRegion
390 return UpdateRegionMapping (
391 MemoryRegion
->VirtualBase
,
392 MemoryRegion
->Length
,
393 ArmMemoryAttributeToPageAttribute (MemoryRegion
->Attributes
) | TT_AF
,
402 GcdAttributeToPageAttribute (
403 IN UINT64 GcdAttributes
406 UINT64 PageAttributes
;
408 switch (GcdAttributes
& EFI_MEMORY_CACHETYPE_MASK
) {
410 PageAttributes
= TT_ATTR_INDX_DEVICE_MEMORY
;
413 PageAttributes
= TT_ATTR_INDX_MEMORY_NON_CACHEABLE
;
416 PageAttributes
= TT_ATTR_INDX_MEMORY_WRITE_THROUGH
| TT_SH_INNER_SHAREABLE
;
419 PageAttributes
= TT_ATTR_INDX_MEMORY_WRITE_BACK
| TT_SH_INNER_SHAREABLE
;
422 PageAttributes
= TT_ATTR_INDX_MASK
;
426 if (((GcdAttributes
& EFI_MEMORY_XP
) != 0) ||
427 ((GcdAttributes
& EFI_MEMORY_CACHETYPE_MASK
) == EFI_MEMORY_UC
))
429 if (ArmReadCurrentEL () == AARCH64_EL2
) {
430 PageAttributes
|= TT_XN_MASK
;
432 PageAttributes
|= TT_UXN_MASK
| TT_PXN_MASK
;
436 if ((GcdAttributes
& EFI_MEMORY_RO
) != 0) {
437 PageAttributes
|= TT_AP_NO_RO
;
440 return PageAttributes
| TT_AF
;
444 ArmSetMemoryAttributes (
445 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
450 UINT64 PageAttributes
;
451 UINT64 PageAttributeMask
;
453 PageAttributes
= GcdAttributeToPageAttribute (Attributes
);
454 PageAttributeMask
= 0;
456 if ((Attributes
& EFI_MEMORY_CACHETYPE_MASK
) == 0) {
458 // No memory type was set in Attributes, so we are going to update the
461 PageAttributes
&= TT_AP_MASK
| TT_UXN_MASK
| TT_PXN_MASK
;
462 PageAttributeMask
= ~(TT_ADDRESS_MASK_BLOCK_ENTRY
| TT_AP_MASK
|
463 TT_PXN_MASK
| TT_XN_MASK
);
466 return UpdateRegionMapping (
471 ArmGetTTBR0BaseAddress (),
478 SetMemoryRegionAttribute (
479 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
481 IN UINT64 Attributes
,
482 IN UINT64 BlockEntryMask
485 return UpdateRegionMapping (
490 ArmGetTTBR0BaseAddress (),
496 ArmSetMemoryRegionNoExec (
497 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
503 if (ArmReadCurrentEL () == AARCH64_EL1
) {
504 Val
= TT_PXN_MASK
| TT_UXN_MASK
;
509 return SetMemoryRegionAttribute (
513 ~TT_ADDRESS_MASK_BLOCK_ENTRY
518 ArmClearMemoryRegionNoExec (
519 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
525 // XN maps to UXN in the EL1&0 translation regime
526 Mask
= ~(TT_ADDRESS_MASK_BLOCK_ENTRY
| TT_PXN_MASK
| TT_XN_MASK
);
528 return SetMemoryRegionAttribute (
537 ArmSetMemoryRegionReadOnly (
538 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
542 return SetMemoryRegionAttribute (
546 ~TT_ADDRESS_MASK_BLOCK_ENTRY
551 ArmClearMemoryRegionReadOnly (
552 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
556 return SetMemoryRegionAttribute (
560 ~(TT_ADDRESS_MASK_BLOCK_ENTRY
| TT_AP_MASK
)
567 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
568 OUT VOID
**TranslationTableBase OPTIONAL
,
569 OUT UINTN
*TranslationTableSize OPTIONAL
572 VOID
*TranslationTable
;
573 UINTN MaxAddressBits
;
576 UINTN RootTableEntryCount
;
580 if (MemoryTable
== NULL
) {
581 ASSERT (MemoryTable
!= NULL
);
582 return EFI_INVALID_PARAMETER
;
586 // Limit the virtual address space to what we can actually use: UEFI
587 // mandates a 1:1 mapping, so no point in making the virtual address
588 // space larger than the physical address space. We also have to take
589 // into account the architectural limitations that result from UEFI's
590 // use of 4 KB pages.
592 MaxAddressBits
= MIN (ArmGetPhysicalAddressBits (), MAX_VA_BITS
);
593 MaxAddress
= LShiftU64 (1ULL, MaxAddressBits
) - 1;
595 T0SZ
= 64 - MaxAddressBits
;
596 RootTableEntryCount
= GetRootTableEntryCount (T0SZ
);
599 // Set TCR that allows us to retrieve T0SZ in the subsequent functions
601 // Ideally we will be running at EL2, but should support EL1 as well.
602 // UEFI should not run at EL3.
603 if (ArmReadCurrentEL () == AARCH64_EL2
) {
604 // Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
605 TCR
= T0SZ
| (1UL << 31) | (1UL << 23) | TCR_TG0_4KB
;
607 // Set the Physical Address Size using MaxAddress
608 if (MaxAddress
< SIZE_4GB
) {
610 } else if (MaxAddress
< SIZE_64GB
) {
612 } else if (MaxAddress
< SIZE_1TB
) {
614 } else if (MaxAddress
< SIZE_4TB
) {
616 } else if (MaxAddress
< SIZE_16TB
) {
618 } else if (MaxAddress
< SIZE_256TB
) {
623 "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
626 ASSERT (0); // Bigger than 48-bit memory space are not supported
627 return EFI_UNSUPPORTED
;
629 } else if (ArmReadCurrentEL () == AARCH64_EL1
) {
630 // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.
631 TCR
= T0SZ
| TCR_TG0_4KB
| TCR_TG1_4KB
| TCR_EPD1
;
633 // Set the Physical Address Size using MaxAddress
634 if (MaxAddress
< SIZE_4GB
) {
636 } else if (MaxAddress
< SIZE_64GB
) {
638 } else if (MaxAddress
< SIZE_1TB
) {
640 } else if (MaxAddress
< SIZE_4TB
) {
642 } else if (MaxAddress
< SIZE_16TB
) {
644 } else if (MaxAddress
< SIZE_256TB
) {
645 TCR
|= TCR_IPS_256TB
;
649 "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
652 ASSERT (0); // Bigger than 48-bit memory space are not supported
653 return EFI_UNSUPPORTED
;
656 ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
657 return EFI_UNSUPPORTED
;
661 // Translation table walks are always cache coherent on ARMv8-A, so cache
662 // maintenance on page tables is never needed. Since there is a risk of
663 // loss of coherency when using mismatched attributes, and given that memory
664 // is mapped cacheable except for extraordinary cases (such as non-coherent
665 // DMA), have the page table walker perform cached accesses as well, and
666 // assert below that matches the attributes we use for CPU accesses to
669 TCR
|= TCR_SH_INNER_SHAREABLE
|
670 TCR_RGN_OUTER_WRITE_BACK_ALLOC
|
671 TCR_RGN_INNER_WRITE_BACK_ALLOC
;
676 // Allocate pages for translation table
677 TranslationTable
= AllocatePages (1);
678 if (TranslationTable
== NULL
) {
679 return EFI_OUT_OF_RESOURCES
;
682 if (TranslationTableBase
!= NULL
) {
683 *TranslationTableBase
= TranslationTable
;
686 if (TranslationTableSize
!= NULL
) {
687 *TranslationTableSize
= RootTableEntryCount
* sizeof (UINT64
);
690 if (!ArmMmuEnabled ()) {
692 // Make sure we are not inadvertently hitting in the caches
693 // when populating the page tables.
695 InvalidateDataCacheRange (
697 RootTableEntryCount
* sizeof (UINT64
)
701 ZeroMem (TranslationTable
, RootTableEntryCount
* sizeof (UINT64
));
703 while (MemoryTable
->Length
!= 0) {
704 Status
= FillTranslationTable (TranslationTable
, MemoryTable
);
705 if (EFI_ERROR (Status
)) {
706 goto FreeTranslationTable
;
713 // EFI_MEMORY_UC ==> MAIR_ATTR_DEVICE_MEMORY
714 // EFI_MEMORY_WC ==> MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE
715 // EFI_MEMORY_WT ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH
716 // EFI_MEMORY_WB ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK
719 MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY
, MAIR_ATTR_DEVICE_MEMORY
) |
720 MAIR_ATTR (TT_ATTR_INDX_MEMORY_NON_CACHEABLE
, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE
) |
721 MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_THROUGH
, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH
) |
722 MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK
, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK
)
725 ArmSetTTBR0 (TranslationTable
);
727 if (!ArmMmuEnabled ()) {
728 ArmDisableAlignmentCheck ();
729 ArmEnableStackAlignmentCheck ();
730 ArmEnableInstructionCache ();
731 ArmEnableDataCache ();
738 FreeTranslationTable
:
739 FreePages (TranslationTable
, 1);
745 ArmMmuBaseLibConstructor (
749 extern UINT32 ArmReplaceLiveTranslationEntrySize
;
752 // The ArmReplaceLiveTranslationEntry () helper function may be invoked
753 // with the MMU off so we have to ensure that it gets cleaned to the PoC
755 WriteBackDataCacheRange (
756 (VOID
*)(UINTN
)ArmReplaceLiveTranslationEntry
,
757 ArmReplaceLiveTranslationEntrySize
760 return RETURN_SUCCESS
;