2 * File managing the MMU for ARMv7 architecture
4 * Copyright (c) 2011-2016, ARM Limited. All rights reserved.
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Chipset/ArmV7.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/CacheMaintenanceLib.h>
20 #include <Library/MemoryAllocationLib.h>
21 #include <Library/ArmLib.h>
22 #include <Library/BaseLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/PcdLib.h>
26 #define ID_MMFR0_SHARELVL_SHIFT 12
27 #define ID_MMFR0_SHARELVL_MASK 0xf
28 #define ID_MMFR0_SHARELVL_ONE 0
29 #define ID_MMFR0_SHARELVL_TWO 1
31 #define ID_MMFR0_INNERSHR_SHIFT 28
32 #define ID_MMFR0_INNERSHR_MASK 0xf
33 #define ID_MMFR0_OUTERSHR_SHIFT 8
34 #define ID_MMFR0_OUTERSHR_MASK 0xf
36 #define ID_MMFR0_SHR_IMP_UNCACHED 0
37 #define ID_MMFR0_SHR_IMP_HW_COHERENT 1
38 #define ID_MMFR0_SHR_IGNORED 0xf
40 #define __EFI_MEMORY_RWX 0 // no restrictions
42 #define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \
62 ConvertSectionAttributesToPageAttributes (
63 IN UINT32 SectionAttributes
,
64 IN BOOLEAN IsLargePage
67 UINT32 PageAttributes
;
70 PageAttributes
|= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes
, IsLargePage
);
71 PageAttributes
|= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes
);
72 PageAttributes
|= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes
, IsLargePage
);
73 PageAttributes
|= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes
);
74 PageAttributes
|= TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes
);
76 return PageAttributes
;
81 PreferNonshareableMemory (
88 if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride
)) {
93 // Check whether the innermost level of shareability (the level we will use
94 // by default to map normal memory) is implemented with hardware coherency
95 // support. Otherwise, revert to mapping as non-shareable.
97 Mmfr
= ArmReadIdMmfr0 ();
98 switch ((Mmfr
>> ID_MMFR0_SHARELVL_SHIFT
) & ID_MMFR0_SHARELVL_MASK
) {
99 case ID_MMFR0_SHARELVL_ONE
:
100 // one level of shareability
101 Val
= (Mmfr
>> ID_MMFR0_OUTERSHR_SHIFT
) & ID_MMFR0_OUTERSHR_MASK
;
103 case ID_MMFR0_SHARELVL_TWO
:
104 // two levels of shareability
105 Val
= (Mmfr
>> ID_MMFR0_INNERSHR_SHIFT
) & ID_MMFR0_INNERSHR_MASK
;
108 // unexpected value -> shareable is the safe option
112 return Val
!= ID_MMFR0_SHR_IMP_HW_COHERENT
;
117 PopulateLevel2PageTable (
118 IN UINT32
*SectionEntry
,
119 IN UINT32 PhysicalBase
,
120 IN UINT32 RemainLength
,
121 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
127 UINT32 PageAttributes
;
128 UINT32 SectionDescriptor
;
129 UINT32 TranslationTable
;
130 UINT32 BaseSectionAddress
;
131 UINT32 FirstPageOffset
;
133 switch (Attributes
) {
134 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
:
135 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
:
136 PageAttributes
= TT_DESCRIPTOR_PAGE_WRITE_BACK
;
138 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
:
139 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
:
140 PageAttributes
= TT_DESCRIPTOR_PAGE_WRITE_THROUGH
;
142 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
:
143 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
:
144 PageAttributes
= TT_DESCRIPTOR_PAGE_DEVICE
;
146 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
:
147 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
:
148 PageAttributes
= TT_DESCRIPTOR_PAGE_UNCACHED
;
151 PageAttributes
= TT_DESCRIPTOR_PAGE_UNCACHED
;
155 if (PreferNonshareableMemory ()) {
156 PageAttributes
&= ~TT_DESCRIPTOR_PAGE_S_SHARED
;
159 // Check if the Section Entry has already been populated. Otherwise attach a
160 // Level 2 Translation Table to it
161 if (*SectionEntry
!= 0) {
162 // The entry must be a page table. Otherwise it exists an overlapping in the memory map
163 if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry
)) {
164 TranslationTable
= *SectionEntry
& TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK
;
165 } else if ((*SectionEntry
& TT_DESCRIPTOR_SECTION_TYPE_MASK
) == TT_DESCRIPTOR_SECTION_TYPE_SECTION
) {
166 // Case where a virtual memory map descriptor overlapped a section entry
168 // Allocate a Level2 Page Table for this Section
169 TranslationTable
= (UINTN
)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE
+ TRANSLATION_TABLE_PAGE_ALIGNMENT
));
170 TranslationTable
= ((UINTN
)TranslationTable
+ TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK
) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK
;
172 // Translate the Section Descriptor into Page Descriptor
173 SectionDescriptor
= TT_DESCRIPTOR_PAGE_TYPE_PAGE
| ConvertSectionAttributesToPageAttributes (*SectionEntry
, FALSE
);
175 BaseSectionAddress
= TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry
);
177 // Populate the new Level2 Page Table for the section
178 PageEntry
= (UINT32
*)TranslationTable
;
179 for (Index
= 0; Index
< TRANSLATION_TABLE_PAGE_COUNT
; Index
++) {
180 PageEntry
[Index
] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress
+ (Index
<< 12)) | SectionDescriptor
;
183 // Overwrite the section entry to point to the new Level2 Translation Table
184 *SectionEntry
= (TranslationTable
& TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK
) |
185 (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes
) ? (1 << 3) : 0) |
186 TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE
;
188 // We do not support the other section type (16MB Section)
193 TranslationTable
= (UINTN
)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE
+ TRANSLATION_TABLE_PAGE_ALIGNMENT
));
194 TranslationTable
= ((UINTN
)TranslationTable
+ TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK
) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK
;
196 ZeroMem ((VOID
*)TranslationTable
, TRANSLATION_TABLE_PAGE_SIZE
);
198 *SectionEntry
= (TranslationTable
& TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK
) |
199 (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes
) ? (1 << 3) : 0) |
200 TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE
;
203 FirstPageOffset
= (PhysicalBase
& TT_DESCRIPTOR_PAGE_INDEX_MASK
) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT
;
204 PageEntry
= (UINT32
*)TranslationTable
+ FirstPageOffset
;
205 Pages
= RemainLength
/ TT_DESCRIPTOR_PAGE_SIZE
;
207 ASSERT (FirstPageOffset
+ Pages
<= TRANSLATION_TABLE_PAGE_COUNT
);
209 for (Index
= 0; Index
< Pages
; Index
++) {
210 *PageEntry
++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase
) | PageAttributes
;
211 PhysicalBase
+= TT_DESCRIPTOR_PAGE_SIZE
;
218 FillTranslationTable (
219 IN UINT32
*TranslationTable
,
220 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryRegion
223 UINT32
*SectionEntry
;
227 UINT32 PageMapLength
;
229 ASSERT(MemoryRegion
->Length
> 0);
231 if (MemoryRegion
->PhysicalBase
>= SIZE_4GB
) {
235 PhysicalBase
= MemoryRegion
->PhysicalBase
;
236 RemainLength
= MIN(MemoryRegion
->Length
, SIZE_4GB
- PhysicalBase
);
238 switch (MemoryRegion
->Attributes
) {
239 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
:
240 Attributes
= TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
242 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
:
243 Attributes
= TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
245 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
:
246 Attributes
= TT_DESCRIPTOR_SECTION_DEVICE(0);
248 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
:
249 Attributes
= TT_DESCRIPTOR_SECTION_UNCACHED(0);
251 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
:
252 Attributes
= TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
254 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
:
255 Attributes
= TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
257 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
:
258 Attributes
= TT_DESCRIPTOR_SECTION_DEVICE(1);
260 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
:
261 Attributes
= TT_DESCRIPTOR_SECTION_UNCACHED(1);
264 Attributes
= TT_DESCRIPTOR_SECTION_UNCACHED(0);
268 if (PreferNonshareableMemory ()) {
269 Attributes
&= ~TT_DESCRIPTOR_SECTION_S_SHARED
;
272 // Get the first section entry for this mapping
273 SectionEntry
= TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable
, MemoryRegion
->VirtualBase
);
275 while (RemainLength
!= 0) {
276 if (PhysicalBase
% TT_DESCRIPTOR_SECTION_SIZE
== 0 &&
277 RemainLength
>= TT_DESCRIPTOR_SECTION_SIZE
) {
278 // Case: Physical address aligned on the Section Size (1MB) && the length
279 // is greater than the Section Size
280 *SectionEntry
++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase
) | Attributes
;
281 PhysicalBase
+= TT_DESCRIPTOR_SECTION_SIZE
;
282 RemainLength
-= TT_DESCRIPTOR_SECTION_SIZE
;
284 PageMapLength
= MIN (RemainLength
, TT_DESCRIPTOR_SECTION_SIZE
) -
285 (PhysicalBase
% TT_DESCRIPTOR_SECTION_SIZE
);
287 // Case: Physical address aligned on the Section Size (1MB) && the length
288 // does not fill a section
289 // Case: Physical address NOT aligned on the Section Size (1MB)
290 PopulateLevel2PageTable (SectionEntry
++, PhysicalBase
, PageMapLength
,
291 MemoryRegion
->Attributes
);
293 // If it is the last entry
294 if (RemainLength
< TT_DESCRIPTOR_SECTION_SIZE
) {
298 PhysicalBase
+= PageMapLength
;
299 RemainLength
-= PageMapLength
;
307 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
308 OUT VOID
**TranslationTableBase OPTIONAL
,
309 OUT UINTN
*TranslationTableSize OPTIONAL
312 VOID
* TranslationTable
;
313 ARM_MEMORY_REGION_ATTRIBUTES TranslationTableAttribute
;
314 UINT32 TTBRAttributes
;
316 // Allocate pages for translation table.
317 TranslationTable
= AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE
+ TRANSLATION_TABLE_SECTION_ALIGNMENT
));
318 if (TranslationTable
== NULL
) {
319 return RETURN_OUT_OF_RESOURCES
;
321 TranslationTable
= (VOID
*)(((UINTN
)TranslationTable
+ TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK
) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK
);
323 if (TranslationTableBase
!= NULL
) {
324 *TranslationTableBase
= TranslationTable
;
327 if (TranslationTableSize
!= NULL
) {
328 *TranslationTableSize
= TRANSLATION_TABLE_SECTION_SIZE
;
331 ZeroMem (TranslationTable
, TRANSLATION_TABLE_SECTION_SIZE
);
333 // By default, mark the translation table as belonging to a uncached region
334 TranslationTableAttribute
= ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
;
335 while (MemoryTable
->Length
!= 0) {
336 // Find the memory attribute for the Translation Table
337 if (((UINTN
)TranslationTable
>= MemoryTable
->PhysicalBase
) && ((UINTN
)TranslationTable
<= MemoryTable
->PhysicalBase
- 1 + MemoryTable
->Length
)) {
338 TranslationTableAttribute
= MemoryTable
->Attributes
;
341 FillTranslationTable (TranslationTable
, MemoryTable
);
345 // Translate the Memory Attributes into Translation Table Register Attributes
346 if ((TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
) ||
347 (TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
)) {
348 TTBRAttributes
= ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE
: TTBR_NON_CACHEABLE
;
349 } else if ((TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
) ||
350 (TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
)) {
351 TTBRAttributes
= ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC
: TTBR_WRITE_BACK_ALLOC
;
352 } else if ((TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
) ||
353 (TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
)) {
354 TTBRAttributes
= ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH
: TTBR_WRITE_THROUGH
;
356 ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to.
357 return RETURN_UNSUPPORTED
;
360 if (TTBRAttributes
& TTBR_SHAREABLE
) {
361 if (PreferNonshareableMemory ()) {
362 TTBRAttributes
^= TTBR_SHAREABLE
;
365 // Unlike the S bit in the short descriptors, which implies inner shareable
366 // on an implementation that supports two levels, the meaning of the S bit
367 // in the TTBR depends on the NOS bit, which defaults to Outer Shareable.
368 // However, we should only set this bit after we have confirmed that the
369 // implementation supports multiple levels, or else the NOS bit is UNK/SBZP
371 if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) {
372 TTBRAttributes
|= TTBR_NOT_OUTER_SHAREABLE
;
377 ArmCleanInvalidateDataCache ();
378 ArmInvalidateInstructionCache ();
380 ArmDisableDataCache ();
381 ArmDisableInstructionCache();
382 // TLBs are also invalidated when calling ArmDisableMmu()
385 // Make sure nothing sneaked into the cache
386 ArmCleanInvalidateDataCache ();
387 ArmInvalidateInstructionCache ();
389 ArmSetTTBR0 ((VOID
*)(UINTN
)(((UINTN
)TranslationTable
& ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK
) | (TTBRAttributes
& 0x7F)));
392 // The TTBCR register value is undefined at reset in the Non-Secure world.
393 // Writing 0 has the effect of:
394 // Clearing EAE: Use short descriptors, as mandated by specification.
395 // Clearing PD0 and PD1: Translation Table Walk Disable is off.
396 // Clearing N: Perform all translation table walks through TTBR0.
397 // (0 is the default reset value in systems not implementing
398 // the Security Extensions.)
402 ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
403 DOMAIN_ACCESS_CONTROL_NONE(14) |
404 DOMAIN_ACCESS_CONTROL_NONE(13) |
405 DOMAIN_ACCESS_CONTROL_NONE(12) |
406 DOMAIN_ACCESS_CONTROL_NONE(11) |
407 DOMAIN_ACCESS_CONTROL_NONE(10) |
408 DOMAIN_ACCESS_CONTROL_NONE( 9) |
409 DOMAIN_ACCESS_CONTROL_NONE( 8) |
410 DOMAIN_ACCESS_CONTROL_NONE( 7) |
411 DOMAIN_ACCESS_CONTROL_NONE( 6) |
412 DOMAIN_ACCESS_CONTROL_NONE( 5) |
413 DOMAIN_ACCESS_CONTROL_NONE( 4) |
414 DOMAIN_ACCESS_CONTROL_NONE( 3) |
415 DOMAIN_ACCESS_CONTROL_NONE( 2) |
416 DOMAIN_ACCESS_CONTROL_NONE( 1) |
417 DOMAIN_ACCESS_CONTROL_CLIENT(0));
419 ArmEnableInstructionCache();
420 ArmEnableDataCache();
422 return RETURN_SUCCESS
;
427 ConvertSectionToPages (
428 IN EFI_PHYSICAL_ADDRESS BaseAddress
431 UINT32 FirstLevelIdx
;
432 UINT32 SectionDescriptor
;
433 UINT32 PageTableDescriptor
;
434 UINT32 PageDescriptor
;
437 volatile ARM_FIRST_LEVEL_DESCRIPTOR
*FirstLevelTable
;
438 volatile ARM_PAGE_TABLE_ENTRY
*PageTable
;
440 DEBUG ((EFI_D_PAGE
, "Converting section at 0x%x to pages\n", (UINTN
)BaseAddress
));
442 // Obtain page table base
443 FirstLevelTable
= (ARM_FIRST_LEVEL_DESCRIPTOR
*)ArmGetTTBR0BaseAddress ();
445 // Calculate index into first level translation table for start of modification
446 FirstLevelIdx
= TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress
) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT
;
447 ASSERT (FirstLevelIdx
< TRANSLATION_TABLE_SECTION_COUNT
);
449 // Get section attributes and convert to page attributes
450 SectionDescriptor
= FirstLevelTable
[FirstLevelIdx
];
451 PageDescriptor
= TT_DESCRIPTOR_PAGE_TYPE_PAGE
| ConvertSectionAttributesToPageAttributes (SectionDescriptor
, FALSE
);
453 // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
454 PageTable
= (volatile ARM_PAGE_TABLE_ENTRY
*)AllocatePages (1);
455 if (PageTable
== NULL
) {
456 return EFI_OUT_OF_RESOURCES
;
459 // Write the page table entries out
460 for (Index
= 0; Index
< TRANSLATION_TABLE_PAGE_COUNT
; Index
++) {
461 PageTable
[Index
] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress
+ (Index
<< 12)) | PageDescriptor
;
464 // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
465 WriteBackInvalidateDataCacheRange ((VOID
*)PageTable
, TT_DESCRIPTOR_PAGE_SIZE
);
467 // Formulate page table entry, Domain=0, NS=0
468 PageTableDescriptor
= (((UINTN
)PageTable
) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK
) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE
;
470 // Write the page table entry out, replacing section entry
471 FirstLevelTable
[FirstLevelIdx
] = PageTableDescriptor
;
479 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
481 IN UINT64 Attributes
,
482 OUT BOOLEAN
*FlushTlbs OPTIONAL
488 UINT32 FirstLevelIdx
;
490 UINT32 NumPageEntries
;
493 UINT32 PageTableIndex
;
494 UINT32 PageTableEntry
;
495 UINT32 CurrentPageTableEntry
;
498 volatile ARM_FIRST_LEVEL_DESCRIPTOR
*FirstLevelTable
;
499 volatile ARM_PAGE_TABLE_ENTRY
*PageTable
;
501 Status
= EFI_SUCCESS
;
503 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
504 // EntryValue: values at bit positions specified by EntryMask
505 EntryMask
= TT_DESCRIPTOR_PAGE_TYPE_MASK
| TT_DESCRIPTOR_PAGE_AP_MASK
;
506 if (Attributes
& EFI_MEMORY_XP
) {
507 EntryValue
= TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN
;
509 EntryValue
= TT_DESCRIPTOR_PAGE_TYPE_PAGE
;
512 // Although the PI spec is unclear on this, the GCD guarantees that only
513 // one Attribute bit is set at a time, so the order of the conditionals below
514 // is irrelevant. If no memory attribute is specified, we preserve whatever
515 // memory type is set in the page tables, and update the permission attributes
517 if (Attributes
& EFI_MEMORY_UC
) {
518 // modify cacheability attributes
519 EntryMask
|= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK
;
520 // map to strongly ordered
521 EntryValue
|= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED
; // TEX[2:0] = 0, C=0, B=0
522 } else if (Attributes
& EFI_MEMORY_WC
) {
523 // modify cacheability attributes
524 EntryMask
|= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK
;
525 // map to normal non-cachable
526 EntryValue
|= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE
; // TEX [2:0]= 001 = 0x2, B=0, C=0
527 } else if (Attributes
& EFI_MEMORY_WT
) {
528 // modify cacheability attributes
529 EntryMask
|= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK
;
530 // write through with no-allocate
531 EntryValue
|= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC
; // TEX [2:0] = 0, C=1, B=0
532 } else if (Attributes
& EFI_MEMORY_WB
) {
533 // modify cacheability attributes
534 EntryMask
|= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK
;
535 // write back (with allocate)
536 EntryValue
|= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC
; // TEX [2:0] = 001, C=1, B=1
537 } else if (Attributes
& CACHE_ATTRIBUTE_MASK
) {
538 // catch unsupported memory type attributes
540 return EFI_UNSUPPORTED
;
543 if (Attributes
& EFI_MEMORY_RO
) {
544 EntryValue
|= TT_DESCRIPTOR_PAGE_AP_RO_RO
;
546 EntryValue
|= TT_DESCRIPTOR_PAGE_AP_RW_RW
;
549 // Obtain page table base
550 FirstLevelTable
= (ARM_FIRST_LEVEL_DESCRIPTOR
*)ArmGetTTBR0BaseAddress ();
552 // Calculate number of 4KB page table entries to change
553 NumPageEntries
= Length
/ TT_DESCRIPTOR_PAGE_SIZE
;
555 // Iterate for the number of 4KB pages to change
557 for(p
= 0; p
< NumPageEntries
; p
++) {
558 // Calculate index into first level translation table for page table value
560 FirstLevelIdx
= TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress
+ Offset
) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT
;
561 ASSERT (FirstLevelIdx
< TRANSLATION_TABLE_SECTION_COUNT
);
563 // Read the descriptor from the first level page table
564 Descriptor
= FirstLevelTable
[FirstLevelIdx
];
566 // Does this descriptor need to be converted from section entry to 4K pages?
567 if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor
)) {
568 Status
= ConvertSectionToPages (FirstLevelIdx
<< TT_DESCRIPTOR_SECTION_BASE_SHIFT
);
569 if (EFI_ERROR(Status
)) {
574 // Re-read descriptor
575 Descriptor
= FirstLevelTable
[FirstLevelIdx
];
576 if (FlushTlbs
!= NULL
) {
581 // Obtain page table base address
582 PageTable
= (ARM_PAGE_TABLE_ENTRY
*)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor
);
584 // Calculate index into the page table
585 PageTableIndex
= ((BaseAddress
+ Offset
) & TT_DESCRIPTOR_PAGE_INDEX_MASK
) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT
;
586 ASSERT (PageTableIndex
< TRANSLATION_TABLE_PAGE_COUNT
);
589 CurrentPageTableEntry
= PageTable
[PageTableIndex
];
591 // Mask off appropriate fields
592 PageTableEntry
= CurrentPageTableEntry
& ~EntryMask
;
594 // Mask in new attributes and/or permissions
595 PageTableEntry
|= EntryValue
;
597 if (CurrentPageTableEntry
!= PageTableEntry
) {
598 Mva
= (VOID
*)(UINTN
)((((UINTN
)FirstLevelIdx
) << TT_DESCRIPTOR_SECTION_BASE_SHIFT
) + (PageTableIndex
<< TT_DESCRIPTOR_PAGE_BASE_SHIFT
));
600 // Clean/invalidate the cache for this page, but only
601 // if we are modifying the memory type attributes
602 if (((CurrentPageTableEntry
^ PageTableEntry
) & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK
) != 0) {
603 WriteBackInvalidateDataCacheRange (Mva
, TT_DESCRIPTOR_PAGE_SIZE
);
606 // Only need to update if we are changing the entry
607 PageTable
[PageTableIndex
] = PageTableEntry
;
608 ArmUpdateTranslationTableEntry ((VOID
*)&PageTable
[PageTableIndex
], Mva
);
611 Status
= EFI_SUCCESS
;
612 Offset
+= TT_DESCRIPTOR_PAGE_SIZE
;
614 } // End first level translation table loop
621 UpdateSectionEntries (
622 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
627 EFI_STATUS Status
= EFI_SUCCESS
;
630 UINT32 FirstLevelIdx
;
633 UINT32 CurrentDescriptor
;
636 volatile ARM_FIRST_LEVEL_DESCRIPTOR
*FirstLevelTable
;
638 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
639 // EntryValue: values at bit positions specified by EntryMask
641 // Make sure we handle a section range that is unmapped
642 EntryMask
= TT_DESCRIPTOR_SECTION_TYPE_MASK
| TT_DESCRIPTOR_SECTION_XN_MASK
|
643 TT_DESCRIPTOR_SECTION_AP_MASK
;
644 EntryValue
= TT_DESCRIPTOR_SECTION_TYPE_SECTION
;
646 // Although the PI spec is unclear on this, the GCD guarantees that only
647 // one Attribute bit is set at a time, so the order of the conditionals below
648 // is irrelevant. If no memory attribute is specified, we preserve whatever
649 // memory type is set in the page tables, and update the permission attributes
651 if (Attributes
& EFI_MEMORY_UC
) {
652 // modify cacheability attributes
653 EntryMask
|= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK
;
654 // map to strongly ordered
655 EntryValue
|= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED
; // TEX[2:0] = 0, C=0, B=0
656 } else if (Attributes
& EFI_MEMORY_WC
) {
657 // modify cacheability attributes
658 EntryMask
|= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK
;
659 // map to normal non-cachable
660 EntryValue
|= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE
; // TEX [2:0]= 001 = 0x2, B=0, C=0
661 } else if (Attributes
& EFI_MEMORY_WT
) {
662 // modify cacheability attributes
663 EntryMask
|= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK
;
664 // write through with no-allocate
665 EntryValue
|= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC
; // TEX [2:0] = 0, C=1, B=0
666 } else if (Attributes
& EFI_MEMORY_WB
) {
667 // modify cacheability attributes
668 EntryMask
|= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK
;
669 // write back (with allocate)
670 EntryValue
|= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC
; // TEX [2:0] = 001, C=1, B=1
671 } else if (Attributes
& CACHE_ATTRIBUTE_MASK
) {
672 // catch unsupported memory type attributes
674 return EFI_UNSUPPORTED
;
677 if (Attributes
& EFI_MEMORY_RO
) {
678 EntryValue
|= TT_DESCRIPTOR_SECTION_AP_RO_RO
;
680 EntryValue
|= TT_DESCRIPTOR_SECTION_AP_RW_RW
;
683 if (Attributes
& EFI_MEMORY_XP
) {
684 EntryValue
|= TT_DESCRIPTOR_SECTION_XN_MASK
;
687 // obtain page table base
688 FirstLevelTable
= (ARM_FIRST_LEVEL_DESCRIPTOR
*)ArmGetTTBR0BaseAddress ();
690 // calculate index into first level translation table for start of modification
691 FirstLevelIdx
= TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress
) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT
;
692 ASSERT (FirstLevelIdx
< TRANSLATION_TABLE_SECTION_COUNT
);
694 // calculate number of 1MB first level entries this applies to
695 NumSections
= Length
/ TT_DESCRIPTOR_SECTION_SIZE
;
697 // iterate through each descriptor
698 for(i
=0; i
<NumSections
; i
++) {
699 CurrentDescriptor
= FirstLevelTable
[FirstLevelIdx
+ i
];
701 // has this descriptor already been coverted to pages?
702 if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor
)) {
703 // forward this 1MB range to page table function instead
704 Status
= UpdatePageEntries (
705 (FirstLevelIdx
+ i
) << TT_DESCRIPTOR_SECTION_BASE_SHIFT
,
706 TT_DESCRIPTOR_SECTION_SIZE
,
710 // still a section entry
712 // mask off appropriate fields
713 Descriptor
= CurrentDescriptor
& ~EntryMask
;
715 // mask in new attributes and/or permissions
716 Descriptor
|= EntryValue
;
718 if (CurrentDescriptor
!= Descriptor
) {
719 Mva
= (VOID
*)(UINTN
)(((UINTN
)FirstLevelTable
) << TT_DESCRIPTOR_SECTION_BASE_SHIFT
);
721 // Clean/invalidate the cache for this section, but only
722 // if we are modifying the memory type attributes
723 if (((CurrentDescriptor
^ Descriptor
) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK
) != 0) {
724 WriteBackInvalidateDataCacheRange (Mva
, SIZE_1MB
);
727 // Only need to update if we are changing the descriptor
728 FirstLevelTable
[FirstLevelIdx
+ i
] = Descriptor
;
729 ArmUpdateTranslationTableEntry ((VOID
*)&FirstLevelTable
[FirstLevelIdx
+ i
], Mva
);
732 Status
= EFI_SUCCESS
;
740 ArmSetMemoryAttributes (
741 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
756 if ((BaseAddress
% TT_DESCRIPTOR_SECTION_SIZE
== 0) &&
757 Length
>= TT_DESCRIPTOR_SECTION_SIZE
) {
759 ChunkLength
= Length
- Length
% TT_DESCRIPTOR_SECTION_SIZE
;
762 "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",
763 BaseAddress
, ChunkLength
, Attributes
));
765 Status
= UpdateSectionEntries (BaseAddress
, ChunkLength
, Attributes
);
771 // Process page by page until the next section boundary, but only if
772 // we have more than a section's worth of area to deal with after that.
774 ChunkLength
= TT_DESCRIPTOR_SECTION_SIZE
-
775 (BaseAddress
% TT_DESCRIPTOR_SECTION_SIZE
);
776 if (ChunkLength
+ TT_DESCRIPTOR_SECTION_SIZE
> Length
) {
777 ChunkLength
= Length
;
781 "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n",
782 BaseAddress
, ChunkLength
, Attributes
));
784 Status
= UpdatePageEntries (BaseAddress
, ChunkLength
, Attributes
,
788 if (EFI_ERROR (Status
)) {
792 BaseAddress
+= ChunkLength
;
793 Length
-= ChunkLength
;
803 ArmSetMemoryRegionNoExec (
804 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
808 return ArmSetMemoryAttributes (BaseAddress
, Length
, EFI_MEMORY_XP
);
812 ArmClearMemoryRegionNoExec (
813 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
817 return ArmSetMemoryAttributes (BaseAddress
, Length
, __EFI_MEMORY_RWX
);
821 ArmSetMemoryRegionReadOnly (
822 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
826 return ArmSetMemoryAttributes (BaseAddress
, Length
, EFI_MEMORY_RO
);
830 ArmClearMemoryRegionReadOnly (
831 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
835 return ArmSetMemoryAttributes (BaseAddress
, Length
, __EFI_MEMORY_RWX
);
840 ArmMmuBaseLibConstructor (
844 return RETURN_SUCCESS
;