ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c

   1 /** @file
   2 *  File managing the MMU for ARMv7 architecture
   3 *
   4 *  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
   5 *
   6 *  SPDX-License-Identifier: BSD-2-Clause-Patent
   7 *
   8 **/
   9
  10 #include <Uefi.h>
  11 #include <Chipset/ArmV7.h>
  12 #include <Library/BaseMemoryLib.h>
  13 #include <Library/CacheMaintenanceLib.h>
  14 #include <Library/MemoryAllocationLib.h>
  15 #include <Library/ArmLib.h>
  16 #include <Library/BaseLib.h>
  17 #include <Library/DebugLib.h>
  18 #include <Library/PcdLib.h>
  19
  20 #define ID_MMFR0_SHARELVL_SHIFT       12
  21 #define ID_MMFR0_SHARELVL_MASK       0xf
  22 #define ID_MMFR0_SHARELVL_ONE          0
  23 #define ID_MMFR0_SHARELVL_TWO          1
  24
  25 #define ID_MMFR0_INNERSHR_SHIFT       28
  26 #define ID_MMFR0_INNERSHR_MASK       0xf
  27 #define ID_MMFR0_OUTERSHR_SHIFT        8
  28 #define ID_MMFR0_OUTERSHR_MASK       0xf
  29
  30 #define ID_MMFR0_SHR_IMP_UNCACHED      0
  31 #define ID_MMFR0_SHR_IMP_HW_COHERENT   1
  32 #define ID_MMFR0_SHR_IGNORED         0xf
  33
  34 #define __EFI_MEMORY_RWX               0    // no restrictions
  35
  36 #define CACHE_ATTRIBUTE_MASK   (EFI_MEMORY_UC | \
  37                                 EFI_MEMORY_WC | \
  38                                 EFI_MEMORY_WT | \
  39                                 EFI_MEMORY_WB | \
  40                                 EFI_MEMORY_UCE | \
  41                                 EFI_MEMORY_WP)
  42
  43 UINTN
  44 EFIAPI
  45 ArmReadIdMmfr0 (
  46   VOID
  47   );
  48
  49 BOOLEAN
  50 EFIAPI
  51 ArmHasMpExtensions (
  52   VOID
  53   );
  54
  55 UINT32
  56 ConvertSectionAttributesToPageAttributes (
  57   IN UINT32   SectionAttributes,
  58   IN BOOLEAN  IsLargePage
  59   )
  60 {
  61   UINT32 PageAttributes;
  62
  63   PageAttributes = 0;
  64   PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);
  65   PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);
  66   PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);
  67   PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes);
  68   PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);
  69
  70   return PageAttributes;
  71 }
  72
  73 STATIC
  74 BOOLEAN
  75 PreferNonshareableMemory (
  76   VOID
  77   )
  78 {
  79   UINTN   Mmfr;
  80   UINTN   Val;
  81
  82   if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {
  83     return TRUE;
  84   }
  85
  86   //
  87   // Check whether the innermost level of shareability (the level we will use
  88   // by default to map normal memory) is implemented with hardware coherency
  89   // support. Otherwise, revert to mapping as non-shareable.
  90   //
  91   Mmfr = ArmReadIdMmfr0 ();
  92   switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {
  93   case ID_MMFR0_SHARELVL_ONE:
  94     // one level of shareability
  95     Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;
  96     break;
  97   case ID_MMFR0_SHARELVL_TWO:
  98     // two levels of shareability
  99     Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;
 100     break;
 101   default:
 102     // unexpected value -> shareable is the safe option
 103     ASSERT (FALSE);
 104     return FALSE;
 105   }
 106   return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;
 107 }
 108
 109 STATIC
 110 VOID
 111 PopulateLevel2PageTable (
 112   IN UINT32                         *SectionEntry,
 113   IN UINT32                         PhysicalBase,
 114   IN UINT32                         RemainLength,
 115   IN ARM_MEMORY_REGION_ATTRIBUTES   Attributes
 116   )
 117 {
 118   UINT32* PageEntry;
 119   UINT32  Pages;
 120   UINT32  Index;
 121   UINT32  PageAttributes;
 122   UINT32  SectionDescriptor;
 123   UINT32  TranslationTable;
 124   UINT32  BaseSectionAddress;
 125   UINT32  FirstPageOffset;
 126
 127   switch (Attributes) {
 128     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
 129     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
 130       PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
 131       break;
 132     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
 133     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
 134       PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
 135       PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;
 136       break;
 137     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
 138     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
 139       PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;
 140       break;
 141     case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
 142     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
 143       PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;
 144       break;
 145     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
 146     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
 147       PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
 148       break;
 149     default:
 150       PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
 151       break;
 152   }
 153
 154   if (PreferNonshareableMemory ()) {
 155     PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;
 156   }
 157
 158   // Check if the Section Entry has already been populated. Otherwise attach a
 159   // Level 2 Translation Table to it
 160   if (*SectionEntry != 0) {
 161     // The entry must be a page table. Otherwise it exists an overlapping in the memory map
 162     if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {
 163       TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;
 164     } else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
 165       // Case where a virtual memory map descriptor overlapped a section entry
 166
 167       // Allocate a Level2 Page Table for this Section
 168       TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));
 169       TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;
 170
 171       // Translate the Section Descriptor into Page Descriptor
 172       SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);
 173
 174       BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);
 175
 176       // Populate the new Level2 Page Table for the section
 177       PageEntry = (UINT32*)TranslationTable;
 178       for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
 179         PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;
 180       }
 181
 182       // Overwrite the section entry to point to the new Level2 Translation Table
 183       *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
 184           (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
 185           TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
 186     } else {
 187       // We do not support the other section type (16MB Section)
 188       ASSERT(0);
 189       return;
 190     }
 191   } else {
 192     TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));
 193     TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;
 194
 195     ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);
 196
 197     *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
 198         (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
 199         TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
 200   }
 201
 202   FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
 203   PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;
 204   Pages     = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;
 205
 206   ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);
 207
 208   for (Index = 0; Index < Pages; Index++) {
 209     *PageEntry++     =  TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;
 210     PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;
 211   }
 212
 213 }
 214
 215 STATIC
 216 VOID
 217 FillTranslationTable (
 218   IN  UINT32                        *TranslationTable,
 219   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
 220   )
 221 {
 222   UINT32  *SectionEntry;
 223   UINT32  Attributes;
 224   UINT32  PhysicalBase;
 225   UINT64  RemainLength;
 226   UINT32  PageMapLength;
 227
 228   ASSERT(MemoryRegion->Length > 0);
 229
 230   if (MemoryRegion->PhysicalBase >= SIZE_4GB) {
 231     return;
 232   }
 233
 234   PhysicalBase = MemoryRegion->PhysicalBase;
 235   RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);
 236
 237   switch (MemoryRegion->Attributes) {
 238     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
 239       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
 240       break;
 241     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
 242       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
 243       Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
 244       break;
 245     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
 246       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
 247       break;
 248     case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
 249       Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);
 250       break;
 251     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
 252       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
 253       break;
 254     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
 255       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
 256       break;
 257     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
 258       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
 259       Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
 260       break;
 261     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
 262       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
 263       break;
 264     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
 265       Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);
 266       break;
 267     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
 268       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
 269       break;
 270     default:
 271       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
 272       break;
 273   }
 274
 275   if (PreferNonshareableMemory ()) {
 276     Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
 277   }
 278
 279   // Get the first section entry for this mapping
 280   SectionEntry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
 281
 282   while (RemainLength != 0) {
 283     if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 &&
 284         RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {
 285       // Case: Physical address aligned on the Section Size (1MB) && the length
 286       // is greater than the Section Size
 287       *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
 288       PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
 289       RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
 290     } else {
 291       PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE -
 292                                          (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE));
 293
 294       // Case: Physical address aligned on the Section Size (1MB) && the length
 295       //       does not fill a section
 296       // Case: Physical address NOT aligned on the Section Size (1MB)
 297       PopulateLevel2PageTable (SectionEntry++, PhysicalBase, PageMapLength,
 298         MemoryRegion->Attributes);
 299
 300       // If it is the last entry
 301       if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {
 302         break;
 303       }
 304
 305       PhysicalBase += PageMapLength;
 306       RemainLength -= PageMapLength;
 307     }
 308   }
 309 }
 310
 311 RETURN_STATUS
 312 EFIAPI
 313 ArmConfigureMmu (
 314   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 315   OUT VOID                         **TranslationTableBase OPTIONAL,
 316   OUT UINTN                         *TranslationTableSize OPTIONAL
 317   )
 318 {
 319   VOID*                         TranslationTable;
 320   ARM_MEMORY_REGION_ATTRIBUTES  TranslationTableAttribute;
 321   UINT32                        TTBRAttributes;
 322
 323   // Allocate pages for translation table.
 324   TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));
 325   if (TranslationTable == NULL) {
 326     return RETURN_OUT_OF_RESOURCES;
 327   }
 328   TranslationTable = (VOID*)(((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK);
 329
 330   if (TranslationTableBase != NULL) {
 331     *TranslationTableBase = TranslationTable;
 332   }
 333
 334   if (TranslationTableSize != NULL) {
 335     *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;
 336   }
 337
 338   ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
 339
 340   // By default, mark the translation table as belonging to a uncached region
 341   TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
 342   while (MemoryTable->Length != 0) {
 343     // Find the memory attribute for the Translation Table
 344     if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
 345       TranslationTableAttribute = MemoryTable->Attributes;
 346     }
 347
 348     FillTranslationTable (TranslationTable, MemoryTable);
 349     MemoryTable++;
 350   }
 351
 352   // Translate the Memory Attributes into Translation Table Register Attributes
 353   if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
 354       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
 355     TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;
 356   } else {
 357     // Page tables must reside in memory mapped as write-back cacheable
 358     ASSERT (0);
 359     return RETURN_UNSUPPORTED;
 360   }
 361
 362   if (TTBRAttributes & TTBR_SHAREABLE) {
 363     if (PreferNonshareableMemory ()) {
 364       TTBRAttributes ^= TTBR_SHAREABLE;
 365     } else {
 366       //
 367       // Unlike the S bit in the short descriptors, which implies inner shareable
 368       // on an implementation that supports two levels, the meaning of the S bit
 369       // in the TTBR depends on the NOS bit, which defaults to Outer Shareable.
 370       // However, we should only set this bit after we have confirmed that the
 371       // implementation supports multiple levels, or else the NOS bit is UNK/SBZP
 372       //
 373       if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) {
 374         TTBRAttributes |= TTBR_NOT_OUTER_SHAREABLE;
 375       }
 376     }
 377   }
 378
 379   ArmCleanInvalidateDataCache ();
 380   ArmInvalidateInstructionCache ();
 381
 382   ArmDisableDataCache ();
 383   ArmDisableInstructionCache();
 384   // TLBs are also invalidated when calling ArmDisableMmu()
 385   ArmDisableMmu ();
 386
 387   // Make sure nothing sneaked into the cache
 388   ArmCleanInvalidateDataCache ();
 389   ArmInvalidateInstructionCache ();
 390
 391   ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
 392
 393   //
 394   // The TTBCR register value is undefined at reset in the Non-Secure world.
 395   // Writing 0 has the effect of:
 396   //   Clearing EAE: Use short descriptors, as mandated by specification.
 397   //   Clearing PD0 and PD1: Translation Table Walk Disable is off.
 398   //   Clearing N: Perform all translation table walks through TTBR0.
 399   //               (0 is the default reset value in systems not implementing
 400   //               the Security Extensions.)
 401   //
 402   ArmSetTTBCR (0);
 403
 404   ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
 405                              DOMAIN_ACCESS_CONTROL_NONE(14) |
 406                              DOMAIN_ACCESS_CONTROL_NONE(13) |
 407                              DOMAIN_ACCESS_CONTROL_NONE(12) |
 408                              DOMAIN_ACCESS_CONTROL_NONE(11) |
 409                              DOMAIN_ACCESS_CONTROL_NONE(10) |
 410                              DOMAIN_ACCESS_CONTROL_NONE( 9) |
 411                              DOMAIN_ACCESS_CONTROL_NONE( 8) |
 412                              DOMAIN_ACCESS_CONTROL_NONE( 7) |
 413                              DOMAIN_ACCESS_CONTROL_NONE( 6) |
 414                              DOMAIN_ACCESS_CONTROL_NONE( 5) |
 415                              DOMAIN_ACCESS_CONTROL_NONE( 4) |
 416                              DOMAIN_ACCESS_CONTROL_NONE( 3) |
 417                              DOMAIN_ACCESS_CONTROL_NONE( 2) |
 418                              DOMAIN_ACCESS_CONTROL_NONE( 1) |
 419                              DOMAIN_ACCESS_CONTROL_CLIENT(0));
 420
 421   ArmEnableInstructionCache();
 422   ArmEnableDataCache();
 423   ArmEnableMmu();
 424   return RETURN_SUCCESS;
 425 }
 426
 427 STATIC
 428 EFI_STATUS
 429 ConvertSectionToPages (
 430   IN EFI_PHYSICAL_ADDRESS  BaseAddress
 431   )
 432 {
 433   UINT32                  FirstLevelIdx;
 434   UINT32                  SectionDescriptor;
 435   UINT32                  PageTableDescriptor;
 436   UINT32                  PageDescriptor;
 437   UINT32                  Index;
 438
 439   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;
 440   volatile ARM_PAGE_TABLE_ENTRY         *PageTable;
 441
 442   DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
 443
 444   // Obtain page table base
 445   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
 446
 447   // Calculate index into first level translation table for start of modification
 448   FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
 449   ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
 450
 451   // Get section attributes and convert to page attributes
 452   SectionDescriptor = FirstLevelTable[FirstLevelIdx];
 453   PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);
 454
 455   // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
 456   PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1);
 457   if (PageTable == NULL) {
 458     return EFI_OUT_OF_RESOURCES;
 459   }
 460
 461   // Write the page table entries out
 462   for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
 463     PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;
 464   }
 465
 466   // Formulate page table entry, Domain=0, NS=0
 467   PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
 468
 469   // Write the page table entry out, replacing section entry
 470   FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
 471
 472   return EFI_SUCCESS;
 473 }
 474
 475 STATIC
 476 EFI_STATUS
 477 UpdatePageEntries (
 478   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 479   IN  UINT64                    Length,
 480   IN  UINT64                    Attributes,
 481   OUT BOOLEAN                   *FlushTlbs OPTIONAL
 482   )
 483 {
 484   EFI_STATUS    Status;
 485   UINT32        EntryValue;
 486   UINT32        EntryMask;
 487   UINT32        FirstLevelIdx;
 488   UINT32        Offset;
 489   UINT32        NumPageEntries;
 490   UINT32        Descriptor;
 491   UINT32        p;
 492   UINT32        PageTableIndex;
 493   UINT32        PageTableEntry;
 494   UINT32        CurrentPageTableEntry;
 495   VOID          *Mva;
 496
 497   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;
 498   volatile ARM_PAGE_TABLE_ENTRY         *PageTable;
 499
 500   Status = EFI_SUCCESS;
 501
 502   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
 503   // EntryValue: values at bit positions specified by EntryMask
 504   EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK;
 505   if (Attributes & EFI_MEMORY_XP) {
 506     EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN;
 507   } else {
 508     EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
 509   }
 510
 511   // Although the PI spec is unclear on this, the GCD guarantees that only
 512   // one Attribute bit is set at a time, so the order of the conditionals below
 513   // is irrelevant. If no memory attribute is specified, we preserve whatever
 514   // memory type is set in the page tables, and update the permission attributes
 515   // only.
 516   if (Attributes & EFI_MEMORY_UC) {
 517     // modify cacheability attributes
 518     EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
 519     // map to strongly ordered
 520     EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
 521   } else if (Attributes & EFI_MEMORY_WC) {
 522     // modify cacheability attributes
 523     EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
 524     // map to normal non-cachable
 525     EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
 526   } else if (Attributes & EFI_MEMORY_WT) {
 527     // modify cacheability attributes
 528     EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
 529     // write through with no-allocate
 530     EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
 531   } else if (Attributes & EFI_MEMORY_WB) {
 532     // modify cacheability attributes
 533     EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
 534     // write back (with allocate)
 535     EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
 536   } else if (Attributes & CACHE_ATTRIBUTE_MASK) {
 537     // catch unsupported memory type attributes
 538     ASSERT (FALSE);
 539     return EFI_UNSUPPORTED;
 540   }
 541
 542   if (Attributes & EFI_MEMORY_RO) {
 543     EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO;
 544   } else {
 545     EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW;
 546   }
 547
 548   // Obtain page table base
 549   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
 550
 551   // Calculate number of 4KB page table entries to change
 552   NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;
 553
 554   // Iterate for the number of 4KB pages to change
 555   Offset = 0;
 556   for(p = 0; p < NumPageEntries; p++) {
 557     // Calculate index into first level translation table for page table value
 558
 559     FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
 560     ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
 561
 562     // Read the descriptor from the first level page table
 563     Descriptor = FirstLevelTable[FirstLevelIdx];
 564
 565     // Does this descriptor need to be converted from section entry to 4K pages?
 566     if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {
 567       Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
 568       if (EFI_ERROR(Status)) {
 569         // Exit for loop
 570         break;
 571       }
 572
 573       // Re-read descriptor
 574       Descriptor = FirstLevelTable[FirstLevelIdx];
 575       if (FlushTlbs != NULL) {
 576         *FlushTlbs = TRUE;
 577       }
 578     }
 579
 580     // Obtain page table base address
 581     PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);
 582
 583     // Calculate index into the page table
 584     PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
 585     ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
 586
 587     // Get the entry
 588     CurrentPageTableEntry = PageTable[PageTableIndex];
 589
 590     // Mask off appropriate fields
 591     PageTableEntry = CurrentPageTableEntry & ~EntryMask;
 592
 593     // Mask in new attributes and/or permissions
 594     PageTableEntry |= EntryValue;
 595
 596     if (CurrentPageTableEntry  != PageTableEntry) {
 597       Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));
 598
 599       // Only need to update if we are changing the entry
 600       PageTable[PageTableIndex] = PageTableEntry;
 601       ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
 602     }
 603
 604     Status = EFI_SUCCESS;
 605     Offset += TT_DESCRIPTOR_PAGE_SIZE;
 606
 607   } // End first level translation table loop
 608
 609   return Status;
 610 }
 611
 612 STATIC
 613 EFI_STATUS
 614 UpdateSectionEntries (
 615   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 616   IN UINT64                    Length,
 617   IN UINT64                    Attributes
 618   )
 619 {
 620   EFI_STATUS    Status = EFI_SUCCESS;
 621   UINT32        EntryMask;
 622   UINT32        EntryValue;
 623   UINT32        FirstLevelIdx;
 624   UINT32        NumSections;
 625   UINT32        i;
 626   UINT32        CurrentDescriptor;
 627   UINT32        Descriptor;
 628   VOID          *Mva;
 629   volatile ARM_FIRST_LEVEL_DESCRIPTOR   *FirstLevelTable;
 630
 631   // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
 632   // EntryValue: values at bit positions specified by EntryMask
 633
 634   // Make sure we handle a section range that is unmapped
 635   EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN_MASK |
 636               TT_DESCRIPTOR_SECTION_AP_MASK;
 637   EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
 638
 639   // Although the PI spec is unclear on this, the GCD guarantees that only
 640   // one Attribute bit is set at a time, so the order of the conditionals below
 641   // is irrelevant. If no memory attribute is specified, we preserve whatever
 642   // memory type is set in the page tables, and update the permission attributes
 643   // only.
 644   if (Attributes & EFI_MEMORY_UC) {
 645     // modify cacheability attributes
 646     EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
 647     // map to strongly ordered
 648     EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
 649   } else if (Attributes & EFI_MEMORY_WC) {
 650     // modify cacheability attributes
 651     EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
 652     // map to normal non-cachable
 653     EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
 654   } else if (Attributes & EFI_MEMORY_WT) {
 655     // modify cacheability attributes
 656     EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
 657     // write through with no-allocate
 658     EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
 659   } else if (Attributes & EFI_MEMORY_WB) {
 660     // modify cacheability attributes
 661     EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
 662     // write back (with allocate)
 663     EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
 664   } else if (Attributes & CACHE_ATTRIBUTE_MASK) {
 665     // catch unsupported memory type attributes
 666     ASSERT (FALSE);
 667     return EFI_UNSUPPORTED;
 668   }
 669
 670   if (Attributes & EFI_MEMORY_RO) {
 671     EntryValue |= TT_DESCRIPTOR_SECTION_AP_RO_RO;
 672   } else {
 673     EntryValue |= TT_DESCRIPTOR_SECTION_AP_RW_RW;
 674   }
 675
 676   if (Attributes & EFI_MEMORY_XP) {
 677     EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK;
 678   }
 679
 680   // obtain page table base
 681   FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
 682
 683   // calculate index into first level translation table for start of modification
 684   FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
 685   ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
 686
 687   // calculate number of 1MB first level entries this applies to
 688   NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;
 689
 690   // iterate through each descriptor
 691   for(i=0; i<NumSections; i++) {
 692     CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
 693
 694     // has this descriptor already been converted to pages?
 695     if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {
 696       // forward this 1MB range to page table function instead
 697       Status = UpdatePageEntries (
 698                  (FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT,
 699                  TT_DESCRIPTOR_SECTION_SIZE,
 700                  Attributes,
 701                  NULL);
 702     } else {
 703       // still a section entry
 704
 705       if (CurrentDescriptor != 0) {
 706         // mask off appropriate fields
 707         Descriptor = CurrentDescriptor & ~EntryMask;
 708       } else {
 709         Descriptor = ((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT;
 710       }
 711
 712       // mask in new attributes and/or permissions
 713       Descriptor |= EntryValue;
 714
 715       if (CurrentDescriptor  != Descriptor) {
 716         Mva = (VOID *)(UINTN)(((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
 717
 718         // Only need to update if we are changing the descriptor
 719         FirstLevelTable[FirstLevelIdx + i] = Descriptor;
 720         ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);
 721       }
 722
 723       Status = EFI_SUCCESS;
 724     }
 725   }
 726
 727   return Status;
 728 }
 729
 730 EFI_STATUS
 731 ArmSetMemoryAttributes (
 732   IN EFI_PHYSICAL_ADDRESS      BaseAddress,
 733   IN UINT64                    Length,
 734   IN UINT64                    Attributes
 735   )
 736 {
 737   EFI_STATUS    Status;
 738   UINT64        ChunkLength;
 739   BOOLEAN       FlushTlbs;
 740
 741   if (BaseAddress > (UINT64)MAX_ADDRESS) {
 742     return EFI_UNSUPPORTED;
 743   }
 744
 745   Length = MIN (Length, (UINT64)MAX_ADDRESS - BaseAddress + 1);
 746   if (Length == 0) {
 747     return EFI_SUCCESS;
 748   }
 749
 750   FlushTlbs = FALSE;
 751   while (Length > 0) {
 752     if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) &&
 753         Length >= TT_DESCRIPTOR_SECTION_SIZE) {
 754
 755       ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE;
 756
 757       DEBUG ((DEBUG_PAGE,
 758         "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",
 759         BaseAddress, ChunkLength, Attributes));
 760
 761       Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes);
 762
 763       FlushTlbs = TRUE;
 764     } else {
 765
 766       //
 767       // Process page by page until the next section boundary, but only if
 768       // we have more than a section's worth of area to deal with after that.
 769       //
 770       ChunkLength = TT_DESCRIPTOR_SECTION_SIZE -
 771                     (BaseAddress % TT_DESCRIPTOR_SECTION_SIZE);
 772       if (ChunkLength + TT_DESCRIPTOR_SECTION_SIZE > Length) {
 773         ChunkLength = Length;
 774       }
 775
 776       DEBUG ((DEBUG_PAGE,
 777         "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n",
 778         BaseAddress, ChunkLength, Attributes));
 779
 780       Status = UpdatePageEntries (BaseAddress, ChunkLength, Attributes,
 781                  &FlushTlbs);
 782     }
 783
 784     if (EFI_ERROR (Status)) {
 785       break;
 786     }
 787
 788     BaseAddress += ChunkLength;
 789     Length -= ChunkLength;
 790   }
 791
 792   if (FlushTlbs) {
 793     ArmInvalidateTlb ();
 794   }
 795   return Status;
 796 }
 797
 798 EFI_STATUS
 799 ArmSetMemoryRegionNoExec (
 800   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 801   IN  UINT64                    Length
 802   )
 803 {
 804   return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP);
 805 }
 806
 807 EFI_STATUS
 808 ArmClearMemoryRegionNoExec (
 809   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 810   IN  UINT64                    Length
 811   )
 812 {
 813   return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
 814 }
 815
 816 EFI_STATUS
 817 ArmSetMemoryRegionReadOnly (
 818   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 819   IN  UINT64                    Length
 820   )
 821 {
 822   return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);
 823 }
 824
 825 EFI_STATUS
 826 ArmClearMemoryRegionReadOnly (
 827   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 828   IN  UINT64                    Length
 829   )
 830 {
 831   return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
 832 }