ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.h

   1 /** @file
   2 *  Header containing the Xpress-RICH3 PCIe Root Complex specific values
   3 *
   4 *  Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15
  16 #ifndef __XPRESS_RICH3_H__
  17 #define __XPRESS_RICH3_H__
  18
  19 #include <Protocol/CpuIo2.h>
  20 #include <Library/PcdLib.h>
  21
  22 #define PCI_ECAM_BASE       FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress)
  23 #define PCI_ECAM_SIZE       FixedPcdGet64 (PcdPciConfigurationSpaceSize)
  24 #define PCI_IO_BASE         FixedPcdGet64 (PcdPciIoBase)
  25 #define PCI_IO_SIZE         FixedPcdGet64 (PcdPciIoSize)
  26 #define PCI_MEM32_BASE      FixedPcdGet64 (PcdPciMmio32Base)
  27 #define PCI_MEM32_SIZE      FixedPcdGet64 (PcdPciMmio32Size)
  28 #define PCI_MEM64_BASE      FixedPcdGet64 (PcdPciMmio64Base)
  29 #define PCI_MEM64_SIZE      FixedPcdGet64 (PcdPciMmio64Size)
  30
  31 /*
  32  * Bridge Internal Registers
  33  */
  34
  35 // PCIe Available Credit Settings
  36 #define PCIE_VC_CRED                            0x090
  37 // PCIe PCI Standard Configuration Identification Settings registers
  38 #define PCIE_PCI_IDS                            0x098
  39 #define PCIE_PCI_IDS_CLASSCODE_OFFSET           0x4
  40 // PCIe Specific 2 Capabilities Settings
  41 #define PCIE_PEX_SPC2                           0x0d8
  42 // PCIe Windows Settings register
  43 #define PCIE_BAR_WIN                            0x0FC
  44 // Local Processor Interrupt Mask
  45 #define PCIE_IMASK_LOCAL                        0x180
  46
  47 #define PCIE_BAR_WIN_SUPPORT_IO                 BIT0
  48 #define PCIE_BAR_WIN_SUPPORT_IO32               BIT1
  49 #define PCIE_BAR_WIN_SUPPORT_MEM                BIT2
  50 #define PCIE_BAR_WIN_SUPPORT_MEM64              BIT3
  51
  52 #define PCIE_INT_MSI                            BIT28
  53 #define PCIE_INT_A                              BIT24
  54 #define PCIE_INT_B                              BIT25
  55 #define PCIE_INT_C                              BIT26
  56 #define PCIE_INT_D                              BIT27
  57 #define PCIE_INT_INTx                           (PCIE_INT_A | PCIE_INT_B |\
  58                                                  PCIE_INT_C | PCIE_INT_D)
  59
  60 /*
  61  * PCIe Control Registers
  62  */
  63 #define PCIE_CONTROL_RST_CTL     0x1004
  64 #define PCIE_CONTROL_RST_STS     0x1008
  65
  66 /*
  67  * PCI Express Address Translation registers
  68  * All are offsets from PcdPcieControlBaseAddress
  69  */
  70 #define VEXPRESS_ATR_PCIE_WIN0    0x600
  71 #define VEXPRESS_ATR_AXI4_SLV0    0x800
  72 #define VEXPRESS_ATR_AXI4_SLV1    0x820
  73
  74 #define PCI_ATR_ENTRY_SIZE           0x20
  75 #define PCI_ATR_SRC_ADDR_LOW_SIZE    0
  76 #define PCI_ATR_SRC_ADDR_HI          0x4
  77 #define PCI_ATR_TRSL_ADDR_LOW        0x8
  78 #define PCI_ATR_TRSL_ADDR_HI         0xc
  79 #define PCI_ATR_TRSL_PARAM           0x10
  80
  81 #define PCI_ATR_TRSLID_AXIDEVICE     0x420004
  82 #define PCI_ATR_TRSLID_AXIMEMORY     0x4e0004
  83 #define PCI_ATR_TRSLID_PCIE_CONF     0x000001
  84 #define PCI_ATR_TRSLID_PCIE_IO       0x020000
  85 #define PCI_ATR_TRSLID_PCIE_MEMORY   0x000000
  86
  87 #define PCIE_CONTROL_RST_CTL_RC_REL        (1 << 1)
  88 #define PCIE_CONTROL_RST_CTL_PHY_REL       (1 << 0)
  89 #define PCIE_CONTROL_RST_CTL_RCPHY_REL     (PCIE_CONTROL_RST_CTL_RC_REL | PCIE_CONTROL_RST_CTL_PHY_REL)
  90
  91 #define PCIE_CONTROL_RST_STS_RC_ST         (1 << 2)
  92 #define PCIE_CONTROL_RST_STS_PHY_ST        (1 << 1)
  93 #define PCIE_CONTROL_RST_STS_PLL_ST        (1 << 0)
  94 #define PCIE_CONTROL_RST_STS_RCPHYPLL_OUT  (PCIE_CONTROL_RST_STS_RC_ST | PCIE_CONTROL_RST_STS_PHY_ST | PCIE_CONTROL_RST_STS_PLL_ST)
  95
  96 #define VEXPRESS_BASIC_STATUS       0x18
  97 #define LINK_UP                     0xff
  98
  99 /*
 100  * Initialize Versatile Express PCIe Host Bridge
 101  */
 102 EFI_STATUS
 103 VExpressPciRbInit (
 104   IN EFI_CPU_IO2_PROTOCOL *CpuIo
 105   );
 106
 107 // Does not support neither EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
 108 // nor EFI_PCI_HOST_BRIDGE_MEM64_DECODE
 109 #define PCI_MEMORY_ALLOCATION_ATTRIBUTES    0
 110
 111 #endif