ArmPlatformPkg/ArmVExpressPkg/Include/VExpressMotherBoard.h

   1 /** @file
   2 *  Header defining Versatile Express constants (Base addresses, sizes, flags)
   3 *
   4 *  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
   5 *
   6 *  This program and the accompanying materials
   7 *  are licensed and made available under the terms and conditions of the BSD License
   8 *  which accompanies this distribution.  The full text of the license may be found at
   9 *  http://opensource.org/licenses/bsd-license.php
  10 *
  11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 *
  14 **/
  15
  16 #ifndef __VEXPRESSMOTHERBOARD_H_
  17 #define __VEXPRESSMOTHERBOARD_H_
  18
  19 #include <ArmPlatform.h>
  20
  21 /***********************************************************************************
  22 // Motherboard memory-mapped peripherals
  23 ************************************************************************************/
  24
  25 // Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
  26 #define ARM_VE_SYS_ID_REG                         (ARM_VE_BOARD_PERIPH_BASE + 0x00000)
  27 #define ARM_VE_SYS_SW_REG                         (ARM_VE_BOARD_PERIPH_BASE + 0x00004)
  28 #define ARM_VE_SYS_LED_REG                        (ARM_VE_BOARD_PERIPH_BASE + 0x00008)
  29 #define ARM_VE_SYS_FLAGS_REG                      (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
  30 #define ARM_VE_SYS_FLAGS_SET_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
  31 #define ARM_VE_SYS_FLAGS_CLR_REG                  (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
  32 #define ARM_VE_SYS_FLAGS_NV_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
  33 #define ARM_VE_SYS_FLAGS_NV_SET_REG               (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
  34 #define ARM_VE_SYS_FLAGS_NV_CLR_REG               (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
  35 #define ARM_VE_SYS_FLASH                          (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)
  36 #define ARM_VE_SYS_CFGSWR_REG                     (ARM_VE_BOARD_PERIPH_BASE + 0x00058)
  37 #define ARM_VE_SYS_MISC                           (ARM_VE_BOARD_PERIPH_BASE + 0x00060)
  38 #define ARM_VE_SYS_PROCID0_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
  39 #define ARM_VE_SYS_PROCID1_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
  40 #define ARM_VE_SYS_CFGDATA_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
  41 #define ARM_VE_SYS_CFGCTRL_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
  42 #define ARM_VE_SYS_CFGSTAT_REG                    (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
  43
  44 // SP810 Controller
  45 #ifndef SP810_CTRL_BASE
  46 #define SP810_CTRL_BASE                           (ARM_VE_BOARD_PERIPH_BASE + 0x01000)
  47 #endif
  48
  49 // PL111 Colour LCD Controller - motherboard
  50 #define PL111_CLCD_MOTHERBOARD_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)
  51 #define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID  1
  52
  53 // VRAM offset for the PL111 Colour LCD Controller on the motherboard
  54 #define VRAM_MOTHERBOARD_BASE                     (ARM_VE_SMB_PERIPH_BASE   + 0x00000)
  55
  56 #define ARM_VE_SYS_PROC_ID_HBI                    0xFFF
  57 #define ARM_VE_SYS_PROC_ID_MASK                   (UINT32)(0xFFU << 24)
  58 #define ARM_VE_SYS_PROC_ID_UNSUPPORTED            (UINT32)(0xFFU << 24)
  59 #define ARM_VE_SYS_PROC_ID_CORTEX_A9              (UINT32)(0x0CU << 24)
  60 #define ARM_VE_SYS_PROC_ID_CORTEX_A5              (UINT32)(0x12U << 24)
  61 #define ARM_VE_SYS_PROC_ID_CORTEX_A15             (UINT32)(0x14U << 24)
  62 #define ARM_VE_SYS_PROC_ID_CORTEX_A7              (UINT32)(0x18U << 24)
  63 #define ARM_VE_SYS_PROC_ID_CORTEX_A12             (UINT32)(0x1CU << 24)
  64
  65 // Boot Master Select:
  66 // 0 = Site 1 boot master
  67 // 1 = Site 2 boot master
  68 #define ARM_VE_SYS_MISC_MASTERSITE                (1 << 14)
  69 //
  70 // Sites where the peripheral is fitted
  71 //
  72 #define ARM_VE_UNSUPPORTED                        ~0
  73 #define ARM_VE_MOTHERBOARD_SITE                   0
  74 #define ARM_VE_DAUGHTERBOARD_1_SITE               1
  75 #define ARM_VE_DAUGHTERBOARD_2_SITE               2
  76
  77 #define VIRTUAL_SYS_CFG(site,func)                (((site) << 24) | (func))
  78
  79 //
  80 // System Configuration Control Functions
  81 //
  82 #define SYS_CFG_OSC                               1
  83 #define SYS_CFG_VOLT                              2
  84 #define SYS_CFG_AMP                               3
  85 #define SYS_CFG_TEMP                              4
  86 #define SYS_CFG_RESET                             5
  87 #define SYS_CFG_SCC                               6
  88 #define SYS_CFG_MUXFPGA                           7
  89 #define SYS_CFG_SHUTDOWN                          8
  90 #define SYS_CFG_REBOOT                            9
  91 #define SYS_CFG_DVIMODE                           11
  92 #define SYS_CFG_POWER                             12
  93 // Oscillator for Site 1
  94 #define SYS_CFG_OSC_SITE1                         VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE,SYS_CFG_OSC)
  95 // Oscillator for Site 2
  96 #define SYS_CFG_OSC_SITE2                         VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE,SYS_CFG_OSC)
  97 // Can not access the battery backed-up hardware clock on the Versatile Express motherboard
  98 #define SYS_CFG_RTC                               VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)
  99
 100 //
 101 // System ID
 102 //
 103 // All RTSM VE models have the same System ID : 0x225F500
 104 //
 105 // FVP models have a different System ID.
 106 // Default Base model System ID : 0x00201100
 107 // [31:28] Rev     - Board revision:          0x0     = Rev A
 108 // [27:16] HBI     - HBI board number in BCD: 0x020   = v8 Base Platform
 109 // [15:12] Variant - Build variant of board:  0x1     = Variant B. (GIC 64k map)
 110 // [11:8]  Plat    - Platform type:           0x1     = Model
 111 // [7:0]   FPGA    - FPGA build, BCD coded:   0x00
 112 //
 113 //HBI = 010 = Foundation Model
 114 //HBI = 020 = Base Platform
 115 //
 116 // And specifically, the GIC register banks start at the following
 117 // addresses:
 118 //              Variant = 0             Variant = 1
 119 //GICD          0x2c001000              0x2f000000
 120 //GICC          0x2c002000              0x2c000000
 121 //GICH          0x2c004000              0x2c010000
 122 //GICV          0x2c006000              0x2c020000
 123
 124 #define ARM_FVP_BASE_BOARD_SYS_ID       (0x00200100)
 125 #define ARM_FVP_FOUNDATION_BOARD_SYS_ID (0x00100100)
 126
 127 #define ARM_FVP_SYS_ID_REV_MASK        (UINT32)(0xFUL   << 28)
 128 #define ARM_FVP_SYS_ID_HBI_MASK        (UINT32)(0xFFFUL << 16)
 129 #define ARM_FVP_SYS_ID_VARIANT_MASK    (UINT32)(0xFUL   << 12)
 130 #define ARM_FVP_SYS_ID_PLAT_MASK       (UINT32)(0xFUL   << 8 )
 131 #define ARM_FVP_SYS_ID_FPGA_MASK       (UINT32)(0xFFUL  << 0 )
 132 #define ARM_FVP_GIC_VE_MMAP            0x0
 133 #define ARM_FVP_GIC_BASE_MMAP          (UINT32)(1 << 12)
 134
 135 // The default SYS_IDs. These can be changed when starting the model.
 136 #define ARM_RTSM_SYS_ID                (0x225F500)
 137 #define ARM_FVP_BASE_SYS_ID            (ARM_FVP_BASE_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)
 138 #define ARM_FVP_FOUNDATION_SYS_ID      (ARM_FVP_FOUNDATION_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)
 139
 140 #endif /* VEXPRESSMOTHERBOARD_H_ */