ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.S

   1 //
   2 //  Copyright (c) 2012-2013, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Library/ArmLib.h>
  16
  17 #include <ArmPlatform.h>
  18
  19 .text
  20 .align 2
  21
  22 GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
  23 GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
  24 GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
  25
  26 ASM_PFX(ArmPlatformPeiBootAction):
  27   bx    lr
  28
  29 //UINTN
  30 //ArmPlatformGetCorePosition (
  31 //  IN UINTN MpId
  32 //  );
  33 ASM_PFX(ArmPlatformGetCorePosition):
  34   and   r1, r0, #ARM_CORE_MASK
  35   and   r0, r0, #ARM_CLUSTER_MASK
  36   add   r0, r1, r0, LSR #7
  37   bx    lr
  38
  39 //UINTN
  40 //ArmPlatformIsPrimaryCore (
  41 //  IN UINTN MpId
  42 //  );
  43 ASM_PFX(ArmPlatformIsPrimaryCore):
  44   // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48
  45   // with cpu_id[0:3] and cluster_id[4:7]
  46   LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r1)
  47   ldr   r1, [r1]
  48   lsr   r1, #24
  49
  50   // Shift the SCC value to get the cluster ID at the offset #8
  51   lsl   r2, r1, #4
  52   and   r2, r2, #0xF00
  53
  54   // Keep only the cpu ID from the original SCC
  55   and   r1, r1, #0x0F
  56   // Add the Cluster ID to the Cpu ID
  57   orr   r1, r1, r2
  58
  59   // Keep the Cluster ID and Core ID from the MPID
  60   LoadConstantToReg (ARM_CLUSTER_MASK | ARM_CORE_MASK, r2)
  61   and   r0, r0, r2
  62
  63   // Compare mpid and boot cpu from ARM_SCC_CFGREG48
  64   cmp   r0, r1
  65   moveq r0, #1
  66   movne r0, #0
  67   bx    lr
  68