3 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/IoLib.h>
16 #include <Library/ArmTrustZoneLib.h>
17 #include <Library/ArmPlatformLib.h>
18 #include <Library/DebugLib.h>
19 #include <Library/PcdLib.h>
20 #include <Drivers/PL341Dmc.h>
21 #include <Drivers/PL301Axi.h>
22 #include <Drivers/PL310L2Cache.h>
23 #include <Library/SerialPortLib.h>
25 #define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
28 PL341_DMC_CONFIG DDRTimings
= {
29 .base
= ARM_VE_DMC_BASE
,
30 .phy_ctrl_base
= 0x0, //There is no DDR2 PHY controller on CTA9 test chip
33 .User0Cfg
= 0x7C924924,
34 .User2Cfg
= (TC_UIOLHXC_VALUE
<< TC_UIOLHNC_SHIFT
) | (TC_UIOLHXC_VALUE
<< TC_UIOLHPC_SHIFT
) | (0x1 << TC_UIOHOCT_SHIFT
) | (0x1 << TC_UIOHSTOP_SHIFT
),
51 .MemoryCfg
= DMC_MEMORY_CONFIG_ACTIVE_CHIP_1
| DMC_MEMORY_CONFIG_BURST_4
|
52 DMC_MEMORY_CONFIG_ROW_ADDRESS_15
| DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10
,
53 .MemoryCfg2
= DMC_MEMORY_CFG2_DQM_INIT
| DMC_MEMORY_CFG2_CKE_INIT
|
54 DMC_MEMORY_CFG2_BANK_BITS_3
| DMC_MEMORY_CFG2_MEM_WIDTH_32
,
55 .MemoryCfg3
= 0x00000001,
56 .ChipCfg0
= 0x00010000,
58 .ModeReg
= DDR2_MR_BURST_LENGTH_4
| DDR2_MR_CAS_LATENCY_4
| DDR2_MR_WR_CYCLES_4
,
59 .ExtModeReg
= DDR_EMR_RTT_50R
| (DDR_EMR_ODS_VAL
<< DDR_EMR_ODS_MASK
),
63 Return if Trustzone is supported by your platform
65 A non-zero value must be returned if you want to support a Secure World on your platform.
66 ArmVExpressTrustzoneInit() will later set up the secure regions.
67 This function can return 0 even if Trustzone is supported by your processor. In this case,
68 the platform will continue to run in Secure World.
70 @return A non-zero value if Trustzone supported.
74 ArmPlatformTrustzoneSupported (
78 return (MmioRead32(ARM_VE_SYS_CFGRW1_REG
) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK
);
82 Initialize the Secure peripherals and memory regions
84 If Trustzone is supported by your platform then this function makes the required initialization
85 of the secure peripherals and memory regions.
88 VOID
ArmPlatformTrustzoneInit(VOID
) {
90 // Setup TZ Protection Controller
93 // Set Non Secure access for all devices
94 TZPCSetDecProtBits(ARM_VE_TZPC_BASE
, TZPC_DECPROT_0
, 0xFFFFFFFF);
95 TZPCSetDecProtBits(ARM_VE_TZPC_BASE
, TZPC_DECPROT_1
, 0xFFFFFFFF);
96 TZPCSetDecProtBits(ARM_VE_TZPC_BASE
, TZPC_DECPROT_2
, 0xFFFFFFFF);
98 // Remove Non secure access to secure devices
99 TZPCClearDecProtBits(ARM_VE_TZPC_BASE
, TZPC_DECPROT_0
,
100 ARM_VE_DECPROT_BIT_TZPC
| ARM_VE_DECPROT_BIT_DMC_TZASC
| ARM_VE_DECPROT_BIT_NMC_TZASC
| ARM_VE_DECPROT_BIT_SMC_TZASC
);
102 TZPCClearDecProtBits(ARM_VE_TZPC_BASE
, TZPC_DECPROT_2
,
103 ARM_VE_DECPROT_BIT_EXT_MAST_TZ
| ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK
| ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK
| ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK
);
107 // Setup TZ Address Space Controller for the SMC. Create 5 Non Secure regions (NOR0, NOR1, SRAM, SMC Peripheral regions)
110 // NOR Flash 0 non secure (BootMon)
111 TZASCSetRegion(ARM_VE_TZASC_BASE
,1,TZASC_REGION_ENABLED
,
112 ARM_VE_SMB_NOR0_BASE
,0,
113 TZASC_REGION_SIZE_64MB
, TZASC_REGION_SECURITY_NSRW
);
115 // NOR Flash 1. The first half of the NOR Flash1 must be secure for the secure firmware (sec_uefi.bin)
116 #if EDK2_ARMVE_SECURE_SYSTEM
117 //Note: Your OS Kernel must be aware of the secure regions before to enable this region
118 TZASCSetRegion(ARM_VE_TZASC_BASE
,2,TZASC_REGION_ENABLED
,
119 ARM_VE_SMB_NOR1_BASE
+ SIZE_32MB
,0,
120 TZASC_REGION_SIZE_32MB
, TZASC_REGION_SECURITY_NSRW
);
122 TZASCSetRegion(ARM_VE_TZASC_BASE
,2,TZASC_REGION_ENABLED
,
123 ARM_VE_SMB_NOR1_BASE
,0,
124 TZASC_REGION_SIZE_64MB
, TZASC_REGION_SECURITY_NSRW
);
127 // Base of SRAM. Only half of SRAM in Non Secure world
128 // First half non secure (16MB) + Second Half secure (16MB) = 32MB of SRAM
129 #if EDK2_ARMVE_SECURE_SYSTEM
130 //Note: Your OS Kernel must be aware of the secure regions before to enable this region
131 TZASCSetRegion(ARM_VE_TZASC_BASE
,3,TZASC_REGION_ENABLED
,
132 ARM_VE_SMB_SRAM_BASE
,0,
133 TZASC_REGION_SIZE_16MB
, TZASC_REGION_SECURITY_NSRW
);
135 TZASCSetRegion(ARM_VE_TZASC_BASE
,3,TZASC_REGION_ENABLED
,
136 ARM_VE_SMB_SRAM_BASE
,0,
137 TZASC_REGION_SIZE_32MB
, TZASC_REGION_SECURITY_NSRW
);
140 // Memory Mapped Peripherals. All in non secure world
141 TZASCSetRegion(ARM_VE_TZASC_BASE
,4,TZASC_REGION_ENABLED
,
142 ARM_VE_SMB_PERIPH_BASE
,0,
143 TZASC_REGION_SIZE_64MB
, TZASC_REGION_SECURITY_NSRW
);
145 // MotherBoard Peripherals and On-chip peripherals.
146 TZASCSetRegion(ARM_VE_TZASC_BASE
,5,TZASC_REGION_ENABLED
,
147 ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE
,0,
148 TZASC_REGION_SIZE_256MB
, TZASC_REGION_SECURITY_NSRW
);
152 Return the current Boot Mode
154 This function returns the boot reason on the platform
156 @return Return the current Boot Mode of the platform
160 ArmPlatformGetBootMode (
164 return BOOT_WITH_FULL_CONFIGURATION
;
168 Remap the memory at 0x0
170 Some platform requires or gives the ability to remap the memory at the address 0x0.
171 This function can do nothing if this feature is not relevant to your platform.
175 ArmPlatformBootRemapping (
179 UINT32 val32
= MmioRead32(ARM_VE_SYS_CFGRW1_REG
); //Scc - CFGRW1
180 // we remap the DRAM to 0x0
181 MmioWrite32(ARM_VE_SYS_CFGRW1_REG
, (val32
& 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM
);
185 Initialize controllers that must setup at the early stage
187 Some peripherals must be initialized in Secure World.
188 For example, some L2x0 requires to be initialized in Secure World
192 ArmPlatformSecInitialize (
195 // The L2x0 controller must be intialize in Secure World
196 L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase
),
197 PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES
,L2x0_LATENCY_8_CYCLES
,L2x0_LATENCY_8_CYCLES
),
198 PL310_DATA_LATENCIES(L2x0_LATENCY_8_CYCLES
,L2x0_LATENCY_8_CYCLES
,L2x0_LATENCY_8_CYCLES
),
199 0,~0, // Use default setting for the Auxiliary Control Register
204 Initialize controllers that must setup in the normal world
206 This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
211 ArmPlatformNormalInitialize (
215 // Nothing to do here
219 Initialize the system (or sometimes called permanent) memory
221 This memory is generally represented by the DRAM.
225 ArmPlatformInitializeSystemMemory (
229 PL341DmcInit(&DDRTimings
);
230 PL301AxiInit(ARM_VE_FAXI_BASE
);