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1 /** @file
2 Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation
3
4 Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PciHostBridge.h"
16
17 //
18 // Hard code: Root Bridge Number within the host bridge
19 // Root Bridge's attribute
20 // Root Bridge's device path
21 // Root Bridge's resource aperture
22 //
23 UINTN RootBridgeNumber[1] = { 1 };
24
25 UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };
26
27 EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
28 {
29 {
30 {
31 {
32 ACPI_DEVICE_PATH,
33 ACPI_DP,
34 {
35 (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
36 (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
37 }
38 },
39 EISA_PNP_ID(0x0A03),
40 0
41 },
42
43 {
44 END_DEVICE_PATH_TYPE,
45 END_ENTIRE_DEVICE_PATH_SUBTYPE,
46 {
47 END_DEVICE_PATH_LENGTH,
48 0
49 }
50 }
51 }
52 }
53 };
54
55 STATIC PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1];
56
57 EFI_HANDLE mDriverImageHandle;
58
59 PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
60 PCI_HOST_BRIDGE_SIGNATURE, // Signature
61 NULL, // HostBridgeHandle
62 0, // RootBridgeNumber
63 {NULL, NULL}, // Head
64 FALSE, // ResourceSubiteed
65 TRUE, // CanRestarted
66 {
67 NotifyPhase,
68 GetNextRootBridge,
69 GetAttributes,
70 StartBusEnumeration,
71 SetBusNumbers,
72 SubmitResources,
73 GetProposedResources,
74 PreprocessController
75 }
76 };
77
78 //
79 // Implementation
80 //
81
82 /**
83 Entry point of this driver
84
85 @param ImageHandle Handle of driver image
86 @param SystemTable Point to EFI_SYSTEM_TABLE
87
88 @retval EFI_ABORTED PCI host bridge not present
89 @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource
90 @retval EFI_DEVICE_ERROR Can not install the protocol instance
91 @retval EFI_SUCCESS Success to initialize the Pci host bridge.
92 **/
93 EFI_STATUS
94 EFIAPI
95 InitializePciHostBridge (
96 IN EFI_HANDLE ImageHandle,
97 IN EFI_SYSTEM_TABLE *SystemTable
98 )
99 {
100 UINT64 MmioAttributes;
101 EFI_STATUS Status;
102 UINTN Loop1;
103 UINTN Loop2;
104 PCI_HOST_BRIDGE_INSTANCE *HostBridge;
105 PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
106
107 if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
108 DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
109 return EFI_ABORTED;
110 }
111
112 mDriverImageHandle = ImageHandle;
113
114 mResAperture[0][0].BusBase = PcdGet32 (PcdPciBusMin);
115 mResAperture[0][0].BusLimit = PcdGet32 (PcdPciBusMax);
116
117 mResAperture[0][0].MemBase = PcdGet32 (PcdPciMmio32Base);
118 mResAperture[0][0].MemLimit = (UINT64)PcdGet32 (PcdPciMmio32Base) +
119 PcdGet32 (PcdPciMmio32Size) - 1;
120
121 mResAperture[0][0].IoBase = PcdGet64 (PcdPciIoBase);
122 mResAperture[0][0].IoLimit = PcdGet64 (PcdPciIoBase) +
123 PcdGet64 (PcdPciIoSize) - 1;
124 mResAperture[0][0].IoTranslation = PcdGet64 (PcdPciIoTranslation);
125
126 //
127 // Add IO and MMIO memory space, so that resources can be allocated in the
128 // EfiPciHostBridgeAllocateResources phase.
129 //
130 Status = gDS->AddIoSpace (
131 EfiGcdIoTypeIo,
132 PcdGet64 (PcdPciIoBase),
133 PcdGet64 (PcdPciIoSize)
134 );
135 ASSERT_EFI_ERROR (Status);
136
137 MmioAttributes = FeaturePcdGet (PcdKludgeMapPciMmioAsCached) ?
138 EFI_MEMORY_WB : EFI_MEMORY_UC;
139
140 Status = gDS->AddMemorySpace (
141 EfiGcdMemoryTypeMemoryMappedIo,
142 PcdGet32 (PcdPciMmio32Base),
143 PcdGet32 (PcdPciMmio32Size),
144 MmioAttributes
145 );
146 if (EFI_ERROR (Status)) {
147 DEBUG ((EFI_D_ERROR, "%a: AddMemorySpace: %r\n", __FUNCTION__, Status));
148 return Status;
149 }
150
151 Status = gDS->SetMemorySpaceAttributes (
152 PcdGet32 (PcdPciMmio32Base),
153 PcdGet32 (PcdPciMmio32Size),
154 MmioAttributes
155 );
156 if (EFI_ERROR (Status)) {
157 DEBUG ((EFI_D_ERROR, "%a: SetMemorySpaceAttributes: %r\n", __FUNCTION__,
158 Status));
159 return Status;
160 }
161
162 //
163 // Create Host Bridge Device Handle
164 //
165 for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {
166 HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);
167 if (HostBridge == NULL) {
168 return EFI_OUT_OF_RESOURCES;
169 }
170
171 HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];
172 InitializeListHead (&HostBridge->Head);
173
174 Status = gBS->InstallMultipleProtocolInterfaces (
175 &HostBridge->HostBridgeHandle,
176 &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
177 NULL
178 );
179 if (EFI_ERROR (Status)) {
180 FreePool (HostBridge);
181 return EFI_DEVICE_ERROR;
182 }
183
184 //
185 // Create Root Bridge Device Handle in this Host Bridge
186 //
187
188 for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {
189 PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));
190 if (PrivateData == NULL) {
191 return EFI_OUT_OF_RESOURCES;
192 }
193
194 PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
195 PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
196
197 RootBridgeConstructor (
198 &PrivateData->Io,
199 HostBridge->HostBridgeHandle,
200 RootBridgeAttribute[Loop1][Loop2],
201 &mResAperture[Loop1][Loop2]
202 );
203
204 Status = gBS->InstallMultipleProtocolInterfaces(
205 &PrivateData->Handle,
206 &gEfiDevicePathProtocolGuid, PrivateData->DevicePath,
207 &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,
208 NULL
209 );
210 if (EFI_ERROR (Status)) {
211 FreePool(PrivateData);
212 return EFI_DEVICE_ERROR;
213 }
214
215 InsertTailList (&HostBridge->Head, &PrivateData->Link);
216 }
217 }
218
219 return EFI_SUCCESS;
220 }
221
222
223 /**
224 These are the notifications from the PCI bus driver that it is about to enter a certain
225 phase of the PCI enumeration process.
226
227 This member function can be used to notify the host bridge driver to perform specific actions,
228 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
229 Eight notification points are defined at this time. See belows:
230 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
231 structures. The PCI enumerator should issue this notification
232 before starting a fresh enumeration process. Enumeration cannot
233 be restarted after sending any other notification such as
234 EfiPciHostBridgeBeginBusAllocation.
235 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
236 required here. This notification can be used to perform any
237 chipset-specific programming.
238 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
239 specific action is required here. This notification can be used to
240 perform any chipset-specific programming.
241 EfiPciHostBridgeBeginResourceAllocation
242 The resource allocation phase is about to begin. No specific
243 action is required here. This notification can be used to perform
244 any chipset-specific programming.
245 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
246 root bridges. These resource settings are returned on the next call to
247 GetProposedResources(). Before calling NotifyPhase() with a Phase of
248 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
249 for gathering I/O and memory requests for
250 all the PCI root bridges and submitting these requests using
251 SubmitResources(). This function pads the resource amount
252 to suit the root bridge hardware, takes care of dependencies between
253 the PCI root bridges, and calls the Global Coherency Domain (GCD)
254 with the allocation request. In the case of padding, the allocated range
255 could be bigger than what was requested.
256 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
257 resources (proposed resources) for all the PCI root bridges. After the
258 hardware is programmed, reassigning resources will not be supported.
259 The bus settings are not affected.
260 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
261 root bridges and resets the I/O and memory apertures to their initial
262 state. The bus settings are not affected. If the request to allocate
263 resources fails, the PCI enumerator can use this notification to
264 deallocate previous resources, adjust the requests, and retry
265 allocation.
266 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
267 required here. This notification can be used to perform any chipsetspecific
268 programming.
269
270 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
271 @param[in] Phase The phase during enumeration
272
273 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
274 is valid for a Phase of EfiPciHostBridgeAllocateResources if
275 SubmitResources() has not been called for one or more
276 PCI root bridges before this call
277 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
278 for a Phase of EfiPciHostBridgeSetResources.
279 @retval EFI_INVALID_PARAMETER Invalid phase parameter
280 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
281 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
282 previously submitted resource requests cannot be fulfilled or
283 were only partially fulfilled.
284 @retval EFI_SUCCESS The notification was accepted without any errors.
285
286 **/
287 EFI_STATUS
288 EFIAPI
289 NotifyPhase(
290 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
291 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
292 )
293 {
294 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
295 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
296 PCI_RESOURCE_TYPE Index;
297 LIST_ENTRY *List;
298 EFI_PHYSICAL_ADDRESS BaseAddress;
299 UINT64 AddrLen;
300 UINTN BitsOfAlignment;
301 EFI_STATUS Status;
302 EFI_STATUS ReturnStatus;
303
304 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
305
306 switch (Phase) {
307
308 case EfiPciHostBridgeBeginEnumeration:
309 if (HostBridgeInstance->CanRestarted) {
310 //
311 // Reset the Each Root Bridge
312 //
313 List = HostBridgeInstance->Head.ForwardLink;
314
315 while (List != &HostBridgeInstance->Head) {
316 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
317 for (Index = TypeIo; Index < TypeMax; Index++) {
318 RootBridgeInstance->ResAllocNode[Index].Type = Index;
319 RootBridgeInstance->ResAllocNode[Index].Base = 0;
320 RootBridgeInstance->ResAllocNode[Index].Length = 0;
321 RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
322 }
323
324 List = List->ForwardLink;
325 }
326
327 HostBridgeInstance->ResourceSubmited = FALSE;
328 HostBridgeInstance->CanRestarted = TRUE;
329 } else {
330 //
331 // Can not restart
332 //
333 return EFI_NOT_READY;
334 }
335 break;
336
337 case EfiPciHostBridgeEndEnumeration:
338 break;
339
340 case EfiPciHostBridgeBeginBusAllocation:
341 //
342 // No specific action is required here, can perform any chipset specific programing
343 //
344 HostBridgeInstance->CanRestarted = FALSE;
345 break;
346
347 case EfiPciHostBridgeEndBusAllocation:
348 //
349 // No specific action is required here, can perform any chipset specific programing
350 //
351 //HostBridgeInstance->CanRestarted = FALSE;
352 break;
353
354 case EfiPciHostBridgeBeginResourceAllocation:
355 //
356 // No specific action is required here, can perform any chipset specific programing
357 //
358 //HostBridgeInstance->CanRestarted = FALSE;
359 break;
360
361 case EfiPciHostBridgeAllocateResources:
362 ReturnStatus = EFI_SUCCESS;
363 if (HostBridgeInstance->ResourceSubmited) {
364 //
365 // Take care of the resource dependencies between the root bridges
366 //
367 List = HostBridgeInstance->Head.ForwardLink;
368
369 while (List != &HostBridgeInstance->Head) {
370 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
371 for (Index = TypeIo; Index < TypeBus; Index++) {
372 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
373
374 AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
375
376 //
377 // Get the number of '1' in Alignment.
378 //
379 BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);
380
381 switch (Index) {
382
383 case TypeIo:
384 //
385 // It is impossible for this chipset to align 0xFFFF for IO16
386 // So clear it
387 //
388 if (BitsOfAlignment >= 16) {
389 BitsOfAlignment = 0;
390 }
391
392 Status = gDS->AllocateIoSpace (
393 EfiGcdAllocateAnySearchBottomUp,
394 EfiGcdIoTypeIo,
395 BitsOfAlignment,
396 AddrLen,
397 &BaseAddress,
398 mDriverImageHandle,
399 NULL
400 );
401
402 if (!EFI_ERROR (Status)) {
403 RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
404 RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
405 } else {
406 ReturnStatus = Status;
407 if (Status != EFI_OUT_OF_RESOURCES) {
408 RootBridgeInstance->ResAllocNode[Index].Length = 0;
409 }
410 }
411
412 break;
413
414
415 case TypeMem32:
416 //
417 // It is impossible for this chipset to align 0xFFFFFFFF for Mem32
418 // So clear it
419 //
420
421 if (BitsOfAlignment >= 32) {
422 BitsOfAlignment = 0;
423 }
424
425 Status = gDS->AllocateMemorySpace (
426 EfiGcdAllocateAnySearchBottomUp,
427 EfiGcdMemoryTypeMemoryMappedIo,
428 BitsOfAlignment,
429 AddrLen,
430 &BaseAddress,
431 mDriverImageHandle,
432 NULL
433 );
434
435 if (!EFI_ERROR (Status)) {
436 // We were able to allocate the PCI memory
437 RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
438 RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
439
440 } else {
441 // Not able to allocate enough PCI memory
442 ReturnStatus = Status;
443
444 if (Status != EFI_OUT_OF_RESOURCES) {
445 RootBridgeInstance->ResAllocNode[Index].Length = 0;
446 }
447 ASSERT (FALSE);
448 }
449 break;
450
451 case TypePMem32:
452 case TypeMem64:
453 case TypePMem64:
454 ReturnStatus = EFI_ABORTED;
455 break;
456 default:
457 ASSERT (FALSE);
458 break;
459 }; //end switch
460 }
461 }
462
463 List = List->ForwardLink;
464 }
465
466 return ReturnStatus;
467
468 } else {
469 return EFI_NOT_READY;
470 }
471 break;
472
473 case EfiPciHostBridgeSetResources:
474 break;
475
476 case EfiPciHostBridgeFreeResources:
477 ReturnStatus = EFI_SUCCESS;
478 List = HostBridgeInstance->Head.ForwardLink;
479 while (List != &HostBridgeInstance->Head) {
480 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
481 for (Index = TypeIo; Index < TypeBus; Index++) {
482 if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {
483 AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
484 BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;
485 switch (Index) {
486
487 case TypeIo:
488 Status = gDS->FreeIoSpace (BaseAddress, AddrLen);
489 if (EFI_ERROR (Status)) {
490 ReturnStatus = Status;
491 }
492 break;
493
494 case TypeMem32:
495 Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);
496 if (EFI_ERROR (Status)) {
497 ReturnStatus = Status;
498 }
499 break;
500
501 case TypePMem32:
502 break;
503
504 case TypeMem64:
505 break;
506
507 case TypePMem64:
508 break;
509
510 default:
511 ASSERT (FALSE);
512 break;
513
514 }; //end switch
515 RootBridgeInstance->ResAllocNode[Index].Type = Index;
516 RootBridgeInstance->ResAllocNode[Index].Base = 0;
517 RootBridgeInstance->ResAllocNode[Index].Length = 0;
518 RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
519 }
520 }
521
522 List = List->ForwardLink;
523 }
524
525 HostBridgeInstance->ResourceSubmited = FALSE;
526 HostBridgeInstance->CanRestarted = TRUE;
527 return ReturnStatus;
528
529 case EfiPciHostBridgeEndResourceAllocation:
530 HostBridgeInstance->CanRestarted = FALSE;
531 break;
532
533 default:
534 return EFI_INVALID_PARAMETER;
535 }
536
537 return EFI_SUCCESS;
538 }
539
540 /**
541 Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
542
543 This function is called multiple times to retrieve the device handles of all the PCI root bridges that
544 are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
545 root bridges. On each call, the handle that was returned by the previous call is passed into the
546 interface, and on output the interface returns the device handle of the next PCI root bridge. The
547 caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
548 for that root bridge. When there are no more PCI root bridges to report, the interface returns
549 EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
550 are returned by this function.
551 For D945 implementation, there is only one root bridge in PCI host bridge.
552
553 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
554 @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
555
556 @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
557 specific Host bridge and return EFI_SUCCESS.
558 @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
559 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
560 returned on a previous call to GetNextRootBridge().
561 **/
562 EFI_STATUS
563 EFIAPI
564 GetNextRootBridge(
565 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
566 IN OUT EFI_HANDLE *RootBridgeHandle
567 )
568 {
569 BOOLEAN NoRootBridge;
570 LIST_ENTRY *List;
571 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
572 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
573
574 NoRootBridge = TRUE;
575 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
576 List = HostBridgeInstance->Head.ForwardLink;
577
578
579 while (List != &HostBridgeInstance->Head) {
580 NoRootBridge = FALSE;
581 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
582 if (*RootBridgeHandle == NULL) {
583 //
584 // Return the first Root Bridge Handle of the Host Bridge
585 //
586 *RootBridgeHandle = RootBridgeInstance->Handle;
587 return EFI_SUCCESS;
588 } else {
589 if (*RootBridgeHandle == RootBridgeInstance->Handle) {
590 //
591 // Get next if have
592 //
593 List = List->ForwardLink;
594 if (List!=&HostBridgeInstance->Head) {
595 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
596 *RootBridgeHandle = RootBridgeInstance->Handle;
597 return EFI_SUCCESS;
598 } else {
599 return EFI_NOT_FOUND;
600 }
601 }
602 }
603
604 List = List->ForwardLink;
605 } //end while
606
607 if (NoRootBridge) {
608 return EFI_NOT_FOUND;
609 } else {
610 return EFI_INVALID_PARAMETER;
611 }
612 }
613
614 /**
615 Returns the allocation attributes of a PCI root bridge.
616
617 The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
618 from one PCI root bridge to another. These attributes are different from the decode-related
619 attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
620 RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
621 handles of all the root bridges that are associated with this host bridge must be obtained by calling
622 GetNextRootBridge(). The attributes are static in the sense that they do not change during or
623 after the enumeration process. The hardware may provide mechanisms to change the attributes on
624 the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
625 installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
626 "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
627 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
628 include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
629 prefetchable memory.
630 Attribute Description
631 ------------------------------------ ----------------------------------------------------------------------
632 EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
633 windows for nonprefetchable and prefetchable memory. A PCI bus
634 driver needs to include requests for prefetchable memory in the
635 nonprefetchable memory pool.
636
637 EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
638 windows. If this bit is not set, the PCI bus driver needs to include
639 requests for a 64-bit memory address in the corresponding 32-bit
640 memory pool.
641
642 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
643 @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
644 EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
645 @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
646
647 @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
648 @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
649 @retval EFI_SUCCESS Success to get attribute of interested root bridge.
650
651 **/
652 EFI_STATUS
653 EFIAPI
654 GetAttributes(
655 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
656 IN EFI_HANDLE RootBridgeHandle,
657 OUT UINT64 *Attributes
658 )
659 {
660 LIST_ENTRY *List;
661 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
662 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
663
664 if (Attributes == NULL) {
665 return EFI_INVALID_PARAMETER;
666 }
667
668 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
669 List = HostBridgeInstance->Head.ForwardLink;
670
671 while (List != &HostBridgeInstance->Head) {
672 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
673 if (RootBridgeHandle == RootBridgeInstance->Handle) {
674 *Attributes = RootBridgeInstance->RootBridgeAttrib;
675 return EFI_SUCCESS;
676 }
677 List = List->ForwardLink;
678 }
679
680 //
681 // RootBridgeHandle is not an EFI_HANDLE
682 // that was returned on a previous call to GetNextRootBridge()
683 //
684 return EFI_INVALID_PARAMETER;
685 }
686
687 /**
688 Sets up the specified PCI root bridge for the bus enumeration process.
689
690 This member function sets up the root bridge for bus enumeration and returns the PCI bus range
691 over which the search should be performed in ACPI 2.0 resource descriptor format.
692
693 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
694 @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
695 @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
696
697 @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
698 @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
699 @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
700
701 **/
702 EFI_STATUS
703 EFIAPI
704 StartBusEnumeration(
705 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
706 IN EFI_HANDLE RootBridgeHandle,
707 OUT VOID **Configuration
708 )
709 {
710 LIST_ENTRY *List;
711 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
712 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
713 VOID *Buffer;
714 UINT8 *Temp;
715 UINT64 BusStart;
716 UINT64 BusEnd;
717
718 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
719 List = HostBridgeInstance->Head.ForwardLink;
720
721 while (List != &HostBridgeInstance->Head) {
722 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
723 if (RootBridgeHandle == RootBridgeInstance->Handle) {
724 //
725 // Set up the Root Bridge for Bus Enumeration
726 //
727 BusStart = RootBridgeInstance->BusBase;
728 BusEnd = RootBridgeInstance->BusLimit;
729 //
730 // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
731 //
732
733 Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
734 if (Buffer == NULL) {
735 return EFI_OUT_OF_RESOURCES;
736 }
737
738 Temp = (UINT8 *)Buffer;
739
740 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;
741 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B;
742 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;
743 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;
744 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;
745 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;
746 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
747 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
748 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
749 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;
750
751 Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
752 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
753 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
754
755 *Configuration = Buffer;
756 return EFI_SUCCESS;
757 }
758 List = List->ForwardLink;
759 }
760
761 return EFI_INVALID_PARAMETER;
762 }
763
764 /**
765 Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
766
767 This member function programs the specified PCI root bridge to decode the bus range that is
768 specified by the input parameter Configuration.
769 The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
770
771 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
772 @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
773 @param[in] Configuration The pointer to the PCI bus resource descriptor
774
775 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
776 @retval EFI_INVALID_PARAMETER Configuration is NULL.
777 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
778 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
779 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
780 bus descriptors.
781 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
782 @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
783 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
784 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
785 @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
786
787 **/
788 EFI_STATUS
789 EFIAPI
790 SetBusNumbers(
791 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
792 IN EFI_HANDLE RootBridgeHandle,
793 IN VOID *Configuration
794 )
795 {
796 LIST_ENTRY *List;
797 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
798 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
799 UINT8 *Ptr;
800 UINTN BusStart;
801 UINTN BusEnd;
802 UINTN BusLen;
803
804 if (Configuration == NULL) {
805 return EFI_INVALID_PARAMETER;
806 }
807
808 Ptr = Configuration;
809
810 //
811 // Check the Configuration is valid
812 //
813 if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
814 return EFI_INVALID_PARAMETER;
815 }
816
817 if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {
818 return EFI_INVALID_PARAMETER;
819 }
820
821 Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
822 if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {
823 return EFI_INVALID_PARAMETER;
824 }
825
826 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
827 List = HostBridgeInstance->Head.ForwardLink;
828
829 Ptr = Configuration;
830
831 while (List != &HostBridgeInstance->Head) {
832 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
833 if (RootBridgeHandle == RootBridgeInstance->Handle) {
834 BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;
835 BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;
836 BusEnd = BusStart + BusLen - 1;
837
838 if (BusStart > BusEnd) {
839 return EFI_INVALID_PARAMETER;
840 }
841
842 if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {
843 return EFI_INVALID_PARAMETER;
844 }
845
846 //
847 // Update the Bus Range
848 //
849 RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;
850 RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;
851 RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;
852
853 //
854 // Program the Root Bridge Hardware
855 //
856
857 return EFI_SUCCESS;
858 }
859
860 List = List->ForwardLink;
861 }
862
863 return EFI_INVALID_PARAMETER;
864 }
865
866
867 /**
868 Submits the I/O and memory resource requirements for the specified PCI root bridge.
869
870 This function is used to submit all the I/O and memory resources that are required by the specified
871 PCI root bridge. The input parameter Configuration is used to specify the following:
872 - The various types of resources that are required
873 - The associated lengths in terms of ACPI 2.0 resource descriptor format
874
875 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
876 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
877 @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
878
879 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
880 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
881 @retval EFI_INVALID_PARAMETER Configuration is NULL.
882 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
883 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
884 not supported by this PCI root bridge. This error will happen if the caller
885 did not combine resources according to Attributes that were returned by
886 GetAllocAttributes().
887 @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
888 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
889 @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
890
891 **/
892 EFI_STATUS
893 EFIAPI
894 SubmitResources(
895 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
896 IN EFI_HANDLE RootBridgeHandle,
897 IN VOID *Configuration
898 )
899 {
900 LIST_ENTRY *List;
901 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
902 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
903 UINT8 *Temp;
904 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
905 UINT64 AddrLen;
906 UINT64 Alignment;
907
908 //
909 // Check the input parameter: Configuration
910 //
911 if (Configuration == NULL) {
912 return EFI_INVALID_PARAMETER;
913 }
914
915 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
916 List = HostBridgeInstance->Head.ForwardLink;
917
918 Temp = (UINT8 *)Configuration;
919 while ( *Temp == 0x8A) {
920 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
921 }
922 if (*Temp != 0x79) {
923 return EFI_INVALID_PARAMETER;
924 }
925
926 Temp = (UINT8 *)Configuration;
927 while (List != &HostBridgeInstance->Head) {
928 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
929 if (RootBridgeHandle == RootBridgeInstance->Handle) {
930 while ( *Temp == 0x8A) {
931 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
932
933 //
934 // Check Address Length
935 //
936 if (Ptr->AddrLen > 0xffffffff) {
937 return EFI_INVALID_PARAMETER;
938 }
939
940 //
941 // Check address range alignment
942 //
943 if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {
944 return EFI_INVALID_PARAMETER;
945 }
946
947 switch (Ptr->ResType) {
948
949 case 0:
950
951 //
952 // Check invalid Address Sapce Granularity
953 //
954 if (Ptr->AddrSpaceGranularity != 32) {
955 return EFI_INVALID_PARAMETER;
956 }
957
958 //
959 // check the memory resource request is supported by PCI root bridge
960 //
961 if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&
962 Ptr->SpecificFlag == 0x06) {
963 return EFI_INVALID_PARAMETER;
964 }
965
966 AddrLen = Ptr->AddrLen;
967 Alignment = Ptr->AddrRangeMax;
968 if (Ptr->AddrSpaceGranularity == 32) {
969 if (Ptr->SpecificFlag == 0x06) {
970 //
971 // Apply from GCD
972 //
973 RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;
974 } else {
975 RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;
976 RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;
977 RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;
978 HostBridgeInstance->ResourceSubmited = TRUE;
979 }
980 }
981
982 if (Ptr->AddrSpaceGranularity == 64) {
983 if (Ptr->SpecificFlag == 0x06) {
984 RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;
985 } else {
986 RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;
987 }
988 }
989 break;
990
991 case 1:
992 AddrLen = (UINTN) Ptr->AddrLen;
993 Alignment = (UINTN) Ptr->AddrRangeMax;
994 RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;
995 RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;
996 RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;
997 HostBridgeInstance->ResourceSubmited = TRUE;
998 break;
999
1000 default:
1001 break;
1002 };
1003
1004 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
1005 }
1006
1007 return EFI_SUCCESS;
1008 }
1009
1010 List = List->ForwardLink;
1011 }
1012
1013 return EFI_INVALID_PARAMETER;
1014 }
1015
1016 /**
1017 Returns the proposed resource settings for the specified PCI root bridge.
1018
1019 This member function returns the proposed resource settings for the specified PCI root bridge. The
1020 proposed resource settings are prepared when NotifyPhase() is called with a Phase of
1021 EfiPciHostBridgeAllocateResources. The output parameter Configuration
1022 specifies the following:
1023 - The various types of resources, excluding bus resources, that are allocated
1024 - The associated lengths in terms of ACPI 2.0 resource descriptor format
1025
1026 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1027 @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
1028 @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
1029
1030 @retval EFI_SUCCESS The requested parameters were returned.
1031 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1032 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
1033 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1034
1035 **/
1036 EFI_STATUS
1037 EFIAPI
1038 GetProposedResources(
1039 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1040 IN EFI_HANDLE RootBridgeHandle,
1041 OUT VOID **Configuration
1042 )
1043 {
1044 LIST_ENTRY *List;
1045 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
1046 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
1047 UINTN Index;
1048 UINTN Number;
1049 VOID *Buffer;
1050 UINT8 *Temp;
1051 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1052 UINT64 ResStatus;
1053
1054 Buffer = NULL;
1055 Number = 0;
1056 //
1057 // Get the Host Bridge Instance from the resource allocation protocol
1058 //
1059 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1060 List = HostBridgeInstance->Head.ForwardLink;
1061
1062 //
1063 // Enumerate the root bridges in this host bridge
1064 //
1065 while (List != &HostBridgeInstance->Head) {
1066 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1067 if (RootBridgeHandle == RootBridgeInstance->Handle) {
1068 for (Index = 0; Index < TypeBus; Index ++) {
1069 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
1070 Number ++;
1071 }
1072 }
1073
1074 if (Number == 0) {
1075 return EFI_INVALID_PARAMETER;
1076 }
1077
1078 Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
1079 if (Buffer == NULL) {
1080 return EFI_OUT_OF_RESOURCES;
1081 }
1082
1083 Temp = Buffer;
1084 for (Index = 0; Index < TypeBus; Index ++) {
1085 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
1086 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
1087 ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
1088
1089 switch (Index) {
1090
1091 case TypeIo:
1092 //
1093 // Io
1094 //
1095 Ptr->Desc = 0x8A;
1096 Ptr->Len = 0x2B;
1097 Ptr->ResType = 1;
1098 Ptr->GenFlag = 0;
1099 Ptr->SpecificFlag = 0;
1100 Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
1101 Ptr->AddrRangeMax = 0;
1102 Ptr->AddrTranslationOffset = \
1103 (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
1104 Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
1105 break;
1106
1107 case TypeMem32:
1108 //
1109 // Memory 32
1110 //
1111 Ptr->Desc = 0x8A;
1112 Ptr->Len = 0x2B;
1113 Ptr->ResType = 0;
1114 Ptr->GenFlag = 0;
1115 Ptr->SpecificFlag = 0;
1116 Ptr->AddrSpaceGranularity = 32;
1117 Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
1118 Ptr->AddrRangeMax = 0;
1119 Ptr->AddrTranslationOffset = \
1120 (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
1121 Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
1122 break;
1123
1124 case TypePMem32:
1125 //
1126 // Prefetch memory 32
1127 //
1128 Ptr->Desc = 0x8A;
1129 Ptr->Len = 0x2B;
1130 Ptr->ResType = 0;
1131 Ptr->GenFlag = 0;
1132 Ptr->SpecificFlag = 6;
1133 Ptr->AddrSpaceGranularity = 32;
1134 Ptr->AddrRangeMin = 0;
1135 Ptr->AddrRangeMax = 0;
1136 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1137 Ptr->AddrLen = 0;
1138 break;
1139
1140 case TypeMem64:
1141 //
1142 // Memory 64
1143 //
1144 Ptr->Desc = 0x8A;
1145 Ptr->Len = 0x2B;
1146 Ptr->ResType = 0;
1147 Ptr->GenFlag = 0;
1148 Ptr->SpecificFlag = 0;
1149 Ptr->AddrSpaceGranularity = 64;
1150 Ptr->AddrRangeMin = 0;
1151 Ptr->AddrRangeMax = 0;
1152 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1153 Ptr->AddrLen = 0;
1154 break;
1155
1156 case TypePMem64:
1157 //
1158 // Prefetch memory 64
1159 //
1160 Ptr->Desc = 0x8A;
1161 Ptr->Len = 0x2B;
1162 Ptr->ResType = 0;
1163 Ptr->GenFlag = 0;
1164 Ptr->SpecificFlag = 6;
1165 Ptr->AddrSpaceGranularity = 64;
1166 Ptr->AddrRangeMin = 0;
1167 Ptr->AddrRangeMax = 0;
1168 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1169 Ptr->AddrLen = 0;
1170 break;
1171 };
1172
1173 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
1174 }
1175 }
1176
1177 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
1178 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
1179
1180 *Configuration = Buffer;
1181
1182 return EFI_SUCCESS;
1183 }
1184
1185 List = List->ForwardLink;
1186 }
1187
1188 return EFI_INVALID_PARAMETER;
1189 }
1190
1191 /**
1192 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
1193 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
1194 PCI controllers before enumeration.
1195
1196 This function is called during the PCI enumeration process. No specific action is expected from this
1197 member function. It allows the host bridge driver to preinitialize individual PCI controllers before
1198 enumeration.
1199
1200 @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1201 @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
1202 InstallProtocolInterface() in the UEFI 2.0 Specification.
1203 @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
1204 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
1205 configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
1206 the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
1207 @param Phase The phase of the PCI device enumeration.
1208
1209 @retval EFI_SUCCESS The requested parameters were returned.
1210 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1211 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
1212 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
1213 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
1214 not enumerate this device, including its child devices if it is a PCI-to-PCI
1215 bridge.
1216
1217 **/
1218 EFI_STATUS
1219 EFIAPI
1220 PreprocessController (
1221 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1222 IN EFI_HANDLE RootBridgeHandle,
1223 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
1224 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
1225 )
1226 {
1227 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
1228 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
1229 LIST_ENTRY *List;
1230
1231 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1232 List = HostBridgeInstance->Head.ForwardLink;
1233
1234 //
1235 // Enumerate the root bridges in this host bridge
1236 //
1237 while (List != &HostBridgeInstance->Head) {
1238 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1239 if (RootBridgeHandle == RootBridgeInstance->Handle) {
1240 break;
1241 }
1242 List = List->ForwardLink;
1243 }
1244 if (List == &HostBridgeInstance->Head) {
1245 return EFI_INVALID_PARAMETER;
1246 }
1247
1248 if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
1249 return EFI_INVALID_PARAMETER;
1250 }
1251
1252 return EFI_SUCCESS;
1253 }
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