2 Serial I/O Port library functions with no library constructor/destructor
4 Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
5 Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Library/DebugLib.h>
18 #include <Library/IoLib.h>
19 #include <Library/PcdLib.h>
21 #include <Drivers/PL011Uart.h>
25 Initialise the serial port to the specified settings.
26 All unspecified settings will be set to the default values.
28 @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
33 PL011UartInitializePort (
36 IN UINT32 ReceiveFifoDepth
,
37 IN EFI_PARITY_TYPE Parity
,
39 IN EFI_STOP_BITS_TYPE StopBits
45 // The BaudRate must be passed
47 return RETURN_INVALID_PARAMETER
;
52 // The PL011 supports a buffer of either 1 or 32 chars. Therefore we can accept
53 // 1 char buffer as the minimum fifo size. Because everything can be rounded down,
54 // there is no maximum fifo size.
55 if (ReceiveFifoDepth
== 0) {
56 LineControl
|= PL011_UARTLCR_H_FEN
;
57 } else if (ReceiveFifoDepth
< 32) {
58 // Nothing else to do. 1 byte fifo is default.
59 } else if (ReceiveFifoDepth
>= 32) {
60 LineControl
|= PL011_UARTLCR_H_FEN
;
69 // Nothing to do. Parity is disabled by default.
72 LineControl
|= (PL011_UARTLCR_H_PEN
| PL011_UARTLCR_H_EPS
);
75 LineControl
|= PL011_UARTLCR_H_PEN
;
78 LineControl
|= (PL011_UARTLCR_H_PEN
| PL011_UARTLCR_H_SPS
| PL011_UARTLCR_H_EPS
);
81 LineControl
|= (PL011_UARTLCR_H_PEN
| PL011_UARTLCR_H_SPS
);
84 return RETURN_INVALID_PARAMETER
;
93 LineControl
|= PL011_UARTLCR_H_WLEN_8
;
96 LineControl
|= PL011_UARTLCR_H_WLEN_7
;
99 LineControl
|= PL011_UARTLCR_H_WLEN_6
;
102 LineControl
|= PL011_UARTLCR_H_WLEN_5
;
105 return RETURN_INVALID_PARAMETER
;
112 case DefaultStopBits
:
114 // Nothing to do. One stop bit is enabled by default.
117 LineControl
|= PL011_UARTLCR_H_STP2
;
119 case OneFiveStopBits
:
120 // Only 1 or 2 stops bits are supported
122 return RETURN_INVALID_PARAMETER
;
125 // Don't send the LineControl value to the PL011 yet,
126 // wait until after the Baud Rate setting.
127 // This ensures we do not mess up the UART settings halfway through
128 // in the rare case when there is an error with the Baud Rate.
133 if (PcdGet32(PL011UartInteger
) != 0) {
134 MmioWrite32 (UartBase
+ UARTIBRD
, PcdGet32(PL011UartInteger
));
135 MmioWrite32 (UartBase
+ UARTFBRD
, PcdGet32(PL011UartFractional
));
137 Divisor
= (PcdGet32 (PL011UartClkInHz
) * 4) / BaudRate
;
138 MmioWrite32 (UartBase
+ UARTIBRD
, Divisor
>> 6);
139 MmioWrite32 (UartBase
+ UARTFBRD
, Divisor
& 0x3F);
142 // No parity, 1 stop, no fifo, 8 data bits
143 MmioWrite32 (UartBase
+ UARTLCR_H
, LineControl
);
145 // Clear any pending errors
146 MmioWrite32 (UartBase
+ UARTECR
, 0);
148 // Enable tx, rx, and uart overall
149 MmioWrite32 (UartBase
+ UARTCR
, PL011_UARTCR_RXE
| PL011_UARTCR_TXE
| PL011_UARTCR_UARTEN
);
151 return RETURN_SUCCESS
;
155 Set the serial device control bits.
157 @param UartBase The base address of the PL011 UART.
158 @param Control Control bits which are to be set on the serial device.
160 @retval EFI_SUCCESS The new control bits were set on the serial device.
161 @retval EFI_UNSUPPORTED The serial device does not support this operation.
162 @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
167 PL011UartSetControl (
173 UINT32 ValidControlBits
;
175 ValidControlBits
= ( EFI_SERIAL_REQUEST_TO_SEND
176 | EFI_SERIAL_DATA_TERMINAL_READY
177 // | EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE // Not implemented yet.
178 // | EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE // Not implemented yet.
179 | EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE
182 if (Control
& (~ValidControlBits
)) {
183 return EFI_UNSUPPORTED
;
186 Bits
= MmioRead32 (UartBase
+ UARTCR
);
188 if (Control
& EFI_SERIAL_REQUEST_TO_SEND
) {
189 Bits
|= PL011_UARTCR_RTS
;
192 if (Control
& EFI_SERIAL_DATA_TERMINAL_READY
) {
193 Bits
|= PL011_UARTCR_DTR
;
196 if (Control
& EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE
) {
197 Bits
|= PL011_UARTCR_LBE
;
200 if (Control
& EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE
) {
201 Bits
|= (PL011_UARTCR_CTSEN
& PL011_UARTCR_RTSEN
);
204 MmioWrite32 (UartBase
+ UARTCR
, Bits
);
206 return RETURN_SUCCESS
;
210 Get the serial device control bits.
212 @param UartBase The base address of the PL011 UART.
213 @param Control Control signals read from the serial device.
215 @retval EFI_SUCCESS The control bits were read from the serial device.
216 @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
221 PL011UartGetControl (
227 UINT32 ControlRegister
;
230 FlagRegister
= MmioRead32 (UartBase
+ UARTFR
);
231 ControlRegister
= MmioRead32 (UartBase
+ UARTCR
);
235 if ((FlagRegister
& PL011_UARTFR_CTS
) == PL011_UARTFR_CTS
) {
236 *Control
|= EFI_SERIAL_CLEAR_TO_SEND
;
239 if ((FlagRegister
& PL011_UARTFR_DSR
) == PL011_UARTFR_DSR
) {
240 *Control
|= EFI_SERIAL_DATA_SET_READY
;
243 if ((FlagRegister
& PL011_UARTFR_RI
) == PL011_UARTFR_RI
) {
244 *Control
|= EFI_SERIAL_RING_INDICATE
;
247 if ((FlagRegister
& PL011_UARTFR_DCD
) == PL011_UARTFR_DCD
) {
248 *Control
|= EFI_SERIAL_CARRIER_DETECT
;
251 if ((ControlRegister
& PL011_UARTCR_RTS
) == PL011_UARTCR_RTS
) {
252 *Control
|= EFI_SERIAL_REQUEST_TO_SEND
;
255 if ((ControlRegister
& PL011_UARTCR_DTR
) == PL011_UARTCR_DTR
) {
256 *Control
|= EFI_SERIAL_DATA_TERMINAL_READY
;
259 if ((FlagRegister
& PL011_UARTFR_RXFE
) == PL011_UARTFR_RXFE
) {
260 *Control
|= EFI_SERIAL_INPUT_BUFFER_EMPTY
;
263 if ((FlagRegister
& PL011_UARTFR_TXFE
) == PL011_UARTFR_TXFE
) {
264 *Control
|= EFI_SERIAL_OUTPUT_BUFFER_EMPTY
;
267 if ((ControlRegister
& (PL011_UARTCR_CTSEN
| PL011_UARTCR_RTSEN
)) == (PL011_UARTCR_CTSEN
| PL011_UARTCR_RTSEN
)) {
268 *Control
|= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE
;
272 // ToDo: Implement EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE
273 if ((ControlRegister
& PL011_UARTCR_LBE
) == PL011_UARTCR_LBE
) {
274 *Control
|= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE
;
277 // ToDo: Implement EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE
278 if (SoftwareLoopbackEnable
) {
279 *Control
|= EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE
;
283 return RETURN_SUCCESS
;
287 Write data to serial device.
289 @param Buffer Point of data buffer which need to be written.
290 @param NumberOfBytes Number of output bytes which are cached in Buffer.
292 @retval 0 Write data failed.
293 @retval !0 Actual number of bytes written to serial device.
301 IN UINTN NumberOfBytes
304 UINT8
* CONST Final
= &Buffer
[NumberOfBytes
];
306 while (Buffer
< Final
) {
307 // Wait until UART able to accept another char
308 while ((MmioRead32 (UartBase
+ UARTFR
) & UART_TX_FULL_FLAG_MASK
));
310 MmioWrite8 (UartBase
+ UARTDR
, *Buffer
++);
313 return NumberOfBytes
;
317 Read data from serial device and save the data in buffer.
319 @param Buffer Point of data buffer which need to be written.
320 @param NumberOfBytes Number of output bytes which are cached in Buffer.
322 @retval 0 Read data failed.
323 @retval !0 Actual number of bytes read from serial device.
331 IN UINTN NumberOfBytes
336 for (Count
= 0; Count
< NumberOfBytes
; Count
++, Buffer
++) {
337 while ((MmioRead32 (UartBase
+ UARTFR
) & UART_RX_EMPTY_FLAG_MASK
) != 0);
338 *Buffer
= MmioRead8 (UartBase
+ UARTDR
);
341 return NumberOfBytes
;
345 Check to see if any data is available to be read from the debug device.
347 @retval EFI_SUCCESS At least one byte of data is available to be read
348 @retval EFI_NOT_READY No data is available to be read
349 @retval EFI_DEVICE_ERROR The serial device is not functioning properly
358 return ((MmioRead32 (UartBase
+ UARTFR
) & UART_RX_EMPTY_FLAG_MASK
) == 0);