2 # Copyright (c) 2011-2012, ARM Limited. All rights reserved.
4 # This program and the accompanying materials
5 # are licensed and made available under the terms and conditions of the BSD License
6 # which accompanies this distribution. The full text of the license may be found at
7 # http://opensource.org/licenses/bsd-license.php
9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #include <AsmMacroIoLib.h>
15 #include <Library/PcdLib.h>
17 #include <Drivers/PL35xSmc.h>
21 #Maintain 8 byte alignment
24 GCC_ASM_EXPORT(PL35xSmcInitialize)
25 GCC_ASM_EXPORT(PL35xSmcSetRefresh)
27 // IN r1 Smc Base Address
28 // IN r2 Smc Configuration Start Address
29 // IN r3 Smc Configuration End Address
30 // NOTE: This code is been called before any stack has been setup. It means some registers
31 // could be overwritten (case of 'r0')
32 ASM_PFX(PL35xSmcInitialize):
33 // While (SmcConfigurationStart < SmcConfigurationEnd)
37 // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
39 str r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]
41 // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
43 str r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]
45 // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
46 ldr r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
49 str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]
52 b ASM_PFX(PL35xSmcInitialize)
54 // IN r1 Smc Base Address
55 // IN r2 Smc Refresh Period 0
56 // IN r3 Smc Refresh Period 1
57 ASM_PFX(PL35xSmcSetRefresh):
58 str r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]
59 str r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]