3 Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/DebugLib.h>
16 #include <Library/IoLib.h>
17 #include <Library/LcdHwLib.h>
18 #include <Library/LcdPlatformLib.h>
19 #include <Library/MemoryAllocationLib.h>
20 #include <Library/PcdLib.h>
24 /**********************************************************************
26 * This file contains all the bits of the Lcd that are
27 * platform independent.
29 **********************************************************************/
38 case LCD_BITS_PER_PIXEL_24
:
41 case LCD_BITS_PER_PIXEL_16_565
:
42 case LCD_BITS_PER_PIXEL_16_555
:
43 case LCD_BITS_PER_PIXEL_12_444
:
46 case LCD_BITS_PER_PIXEL_8
:
47 case LCD_BITS_PER_PIXEL_4
:
48 case LCD_BITS_PER_PIXEL_2
:
49 case LCD_BITS_PER_PIXEL_1
:
59 IN EFI_PHYSICAL_ADDRESS VramBaseAddress
62 // Disable the controller
63 MmioWrite32(HDLCD_REG_COMMAND
, HDLCD_DISABLE
);
65 // Disable all interrupts
66 MmioWrite32(HDLCD_REG_INT_MASK
, 0);
68 // Define start of the VRAM. This never changes for any graphics mode
69 MmioWrite32(HDLCD_REG_FB_BASE
, (UINT32
) VramBaseAddress
);
71 // Setup various registers that never change
72 MmioWrite32(HDLCD_REG_BUS_OPTIONS
, (4 << 8) | HDLCD_BURST_8
);
73 MmioWrite32(HDLCD_REG_POLARITIES
, HDLCD_PXCLK_LOW
| HDLCD_DATA_HIGH
| HDLCD_DATEN_HIGH
| HDLCD_HSYNC_LOW
| HDLCD_VSYNC_HIGH
);
74 MmioWrite32(HDLCD_REG_PIXEL_FORMAT
, HDLCD_LITTLE_ENDIAN
| HDLCD_4BYTES_PER_PIXEL
);
75 MmioWrite32(HDLCD_REG_RED_SELECT
, (0 << 16 | 8 << 8 | 0));
76 MmioWrite32(HDLCD_REG_GREEN_SELECT
, (0 << 16 | 8 << 8 | 8));
77 MmioWrite32(HDLCD_REG_BLUE_SELECT
, (0 << 16 | 8 << 8 | 16));
100 // Set the video mode timings and other relevant information
101 Status
= LcdPlatformGetTimings (ModeNumber
,
102 &HRes
,&HSync
,&HBackPorch
,&HFrontPorch
,
103 &VRes
,&VSync
,&VBackPorch
,&VFrontPorch
);
104 ASSERT_EFI_ERROR (Status
);
105 if (EFI_ERROR( Status
)) {
106 return EFI_DEVICE_ERROR
;
109 Status
= LcdPlatformGetBpp (ModeNumber
,&LcdBpp
);
110 ASSERT_EFI_ERROR (Status
);
111 if (EFI_ERROR( Status
)) {
112 return EFI_DEVICE_ERROR
;
115 BytesPerPixel
= GetBytesPerPixel(LcdBpp
);
117 // Disable the controller
118 MmioWrite32(HDLCD_REG_COMMAND
, HDLCD_DISABLE
);
120 // Update the frame buffer information with the new settings
121 MmioWrite32(HDLCD_REG_FB_LINE_LENGTH
, HRes
* BytesPerPixel
);
122 MmioWrite32(HDLCD_REG_FB_LINE_PITCH
, HRes
* BytesPerPixel
);
123 MmioWrite32(HDLCD_REG_FB_LINE_COUNT
, VRes
- 1);
125 // Set the vertical timing information
126 MmioWrite32(HDLCD_REG_V_SYNC
, VSync
);
127 MmioWrite32(HDLCD_REG_V_BACK_PORCH
, VBackPorch
);
128 MmioWrite32(HDLCD_REG_V_DATA
, VRes
- 1);
129 MmioWrite32(HDLCD_REG_V_FRONT_PORCH
, VFrontPorch
);
131 // Set the horizontal timing information
132 MmioWrite32(HDLCD_REG_H_SYNC
, HSync
);
133 MmioWrite32(HDLCD_REG_H_BACK_PORCH
, HBackPorch
);
134 MmioWrite32(HDLCD_REG_H_DATA
, HRes
- 1);
135 MmioWrite32(HDLCD_REG_H_FRONT_PORCH
, HFrontPorch
);
137 // Enable the controller
138 MmioWrite32(HDLCD_REG_COMMAND
, HDLCD_ENABLE
);
148 // Disable the controller
149 MmioWrite32 (HDLCD_REG_COMMAND
, HDLCD_DISABLE
);