ArmPlatformPkg/Library/HdLcd/HdLcd.h

   1 /** @file
   2
   3  Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>
   4
   5  SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7  **/
   8
   9 #ifndef HDLCD_H_
  10 #define HDLCD_H_
  11
  12 // HDLCD Controller Register Offsets
  13 #define HDLCD_REG_VERSION         ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
  14 #define HDLCD_REG_INT_RAWSTAT     ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
  15 #define HDLCD_REG_INT_CLEAR       ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
  16 #define HDLCD_REG_INT_MASK        ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
  17 #define HDLCD_REG_INT_STATUS      ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
  18 #define HDLCD_REG_FB_BASE         ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
  19 #define HDLCD_REG_FB_LINE_LENGTH  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
  20 #define HDLCD_REG_FB_LINE_COUNT   ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
  21 #define HDLCD_REG_FB_LINE_PITCH   ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
  22 #define HDLCD_REG_BUS_OPTIONS     ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
  23 #define HDLCD_REG_V_SYNC          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
  24 #define HDLCD_REG_V_BACK_PORCH    ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
  25 #define HDLCD_REG_V_DATA          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
  26 #define HDLCD_REG_V_FRONT_PORCH   ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
  27 #define HDLCD_REG_H_SYNC          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
  28 #define HDLCD_REG_H_BACK_PORCH    ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
  29 #define HDLCD_REG_H_DATA          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
  30 #define HDLCD_REG_H_FRONT_PORCH   ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
  31 #define HDLCD_REG_POLARITIES      ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
  32 #define HDLCD_REG_COMMAND         ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
  33 #define HDLCD_REG_PIXEL_FORMAT    ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
  34 #define HDLCD_REG_RED_SELECT      ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
  35 #define HDLCD_REG_GREEN_SELECT    ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
  36 #define HDLCD_REG_BLUE_SELECT     ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
  37
  38 // HDLCD Values of registers
  39
  40 // HDLCD Interrupt mask, clear and status register
  41 #define HDLCD_DMA_END    BIT0                     /* DMA has finished reading a frame */
  42 #define HDLCD_BUS_ERROR  BIT1                     /* DMA bus error */
  43 #define HDLCD_SYNC       BIT2                     /* Vertical sync */
  44 #define HDLCD_UNDERRUN   BIT3                     /* No Data available while DATAEN active */
  45
  46 // CLCD_CONTROL Control register
  47 #define HDLCD_DISABLE  0
  48 #define HDLCD_ENABLE   BIT0
  49
  50 // Bus Options
  51 #define HDLCD_BURST_1   BIT0
  52 #define HDLCD_BURST_2   BIT1
  53 #define HDLCD_BURST_4   BIT2
  54 #define HDLCD_BURST_8   BIT3
  55 #define HDLCD_BURST_16  BIT4
  56
  57 // Polarities - HIGH
  58 #define HDLCD_VSYNC_HIGH  BIT0
  59 #define HDLCD_HSYNC_HIGH  BIT1
  60 #define HDLCD_DATEN_HIGH  BIT2
  61 #define HDLCD_DATA_HIGH   BIT3
  62 #define HDLCD_PXCLK_HIGH  BIT4
  63 // Polarities - LOW (for completion and for ease of understanding the hardware settings)
  64 #define HDLCD_VSYNC_LOW  0
  65 #define HDLCD_HSYNC_LOW  0
  66 #define HDLCD_DATEN_LOW  0
  67 #define HDLCD_DATA_LOW   0
  68 #define HDLCD_PXCLK_LOW  0
  69
  70 // Default polarities
  71 #define HDLCD_DEFAULT_POLARITIES  (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH |        \
  72                                     HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW |      \
  73                                     HDLCD_VSYNC_HIGH)
  74
  75 // Pixel Format
  76 #define HDLCD_LITTLE_ENDIAN  (0 << 31)
  77 #define HDLCD_BIG_ENDIAN     (1 << 31)
  78
  79 // Number of bytes per pixel
  80 #define HDLCD_4BYTES_PER_PIXEL  ((4 - 1) << 3)
  81
  82 #define HDLCD_PRODUCT_ID  0x1CDC
  83
  84 #endif /* HDLCD_H_ */