2 Main file supporting the transition to PEI Core in Normal World for Versatile Express
4 Copyright (c) 2011-2014, ARM Limited. All rights reserved.
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #include <Library/BaseLib.h>
11 #include <Library/CacheMaintenanceLib.h>
12 #include <Library/DebugAgentLib.h>
13 #include <Library/ArmLib.h>
15 #include "PrePeiCore.h"
17 CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi
= { PrePeiCoreTemporaryRamSupport
};
19 CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable
[] = {
21 EFI_PEI_PPI_DESCRIPTOR_PPI
,
22 &gEfiTemporaryRamSupportPpiGuid
,
23 (VOID
*)&mTemporaryRamSupportPpi
29 OUT UINTN
*PpiListSize
,
30 OUT EFI_PEI_PPI_DESCRIPTOR
**PpiList
33 EFI_PEI_PPI_DESCRIPTOR
*PlatformPpiList
;
34 UINTN PlatformPpiListSize
;
36 EFI_PEI_PPI_DESCRIPTOR
*LastPpi
;
38 // Get the Platform PPIs
39 PlatformPpiListSize
= 0;
40 ArmPlatformGetPlatformPpiList (&PlatformPpiListSize
, &PlatformPpiList
);
42 // Copy the Common and Platform PPis in Temporary Memory
43 ListBase
= PcdGet64 (PcdCPUCoresStackBase
);
44 CopyMem ((VOID
*)ListBase
, gCommonPpiTable
, sizeof (gCommonPpiTable
));
45 CopyMem ((VOID
*)(ListBase
+ sizeof (gCommonPpiTable
)), PlatformPpiList
, PlatformPpiListSize
);
47 // Set the Terminate flag on the last PPI entry
48 LastPpi
= (EFI_PEI_PPI_DESCRIPTOR
*)ListBase
+ ((sizeof (gCommonPpiTable
) + PlatformPpiListSize
) / sizeof (EFI_PEI_PPI_DESCRIPTOR
)) - 1;
49 LastPpi
->Flags
|= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
;
51 *PpiList
= (EFI_PEI_PPI_DESCRIPTOR
*)ListBase
;
52 *PpiListSize
= sizeof (gCommonPpiTable
) + PlatformPpiListSize
;
58 IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
61 // Data Cache enabled on Primary core when MMU is enabled.
62 ArmDisableDataCache ();
63 // Invalidate instruction cache
64 ArmInvalidateInstructionCache ();
65 // Enable Instruction Caches on all cores.
66 ArmEnableInstructionCache ();
68 InvalidateDataCacheRange (
69 (VOID
*)(UINTN
)PcdGet64 (PcdCPUCoresStackBase
),
70 PcdGet32 (PcdCPUCorePrimaryStackSize
)
74 // Note: Doesn't have to Enable CPU interface in non-secure world,
75 // as Non-secure interface is already enabled in Secure world.
78 // Write VBAR - The Exception Vector table must be aligned to its requirement
79 // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
80 // 'Align=4K' is defined into your FDF for this module.
81 ASSERT (((UINTN
)PeiVectorTable
& ARM_VECTOR_TABLE_ALIGNMENT
) == 0);
82 ArmWriteVBar ((UINTN
)PeiVectorTable
);
84 // Enable Floating Point
85 if (FixedPcdGet32 (PcdVFPEnabled
)) {
89 // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
91 // If not primary Jump to Secondary Main
92 if (ArmPlatformIsPrimaryCore (MpId
)) {
93 // Initialize the Debug Agent for Source Level Debugging
94 InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC
, NULL
, NULL
);
95 SaveAndSetDebugTimerInterrupt (TRUE
);
97 // Initialize the platform specific controllers
98 ArmPlatformInitialize (MpId
);
100 // Goto primary Main.
101 PrimaryMain (PeiCoreEntryPoint
);
103 SecondaryMain (MpId
);
106 // PEI Core should always load and never return
112 PrePeiCoreTemporaryRamSupport (
113 IN CONST EFI_PEI_SERVICES
**PeiServices
,
114 IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase
,
115 IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase
,
125 HeapSize
= ALIGN_VALUE (CopySize
/ 2, CPU_STACK_ALIGNMENT
);
127 OldHeap
= (VOID
*)(UINTN
)TemporaryMemoryBase
;
128 NewHeap
= (VOID
*)((UINTN
)PermanentMemoryBase
+ (CopySize
- HeapSize
));
130 OldStack
= (VOID
*)((UINTN
)TemporaryMemoryBase
+ HeapSize
);
131 NewStack
= (VOID
*)(UINTN
)PermanentMemoryBase
;
134 // Migrate the temporary memory stack to permanent memory stack.
136 CopyMem (NewStack
, OldStack
, CopySize
- HeapSize
);
139 // Migrate the temporary memory heap to permanent memory heap.
141 CopyMem (NewHeap
, OldHeap
, HeapSize
);
143 SecSwitchStack ((UINTN
)NewStack
- (UINTN
)OldStack
);