ArmPlatformPkg/PrePeiCore/PrePeiCore.c

   1 /** @file
   2   Main file supporting the transition to PEI Core in Normal World for Versatile Express
   3
   4   Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #include <Library/BaseLib.h>
  11 #include <Library/CacheMaintenanceLib.h>
  12 #include <Library/DebugAgentLib.h>
  13 #include <Library/ArmLib.h>
  14
  15 #include "PrePeiCore.h"
  16
  17 CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI  mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };
  18
  19 CONST EFI_PEI_PPI_DESCRIPTOR  gCommonPpiTable[] = {
  20   {
  21     EFI_PEI_PPI_DESCRIPTOR_PPI,
  22     &gEfiTemporaryRamSupportPpiGuid,
  23     (VOID *)&mTemporaryRamSupportPpi
  24   }
  25 };
  26
  27 VOID
  28 CreatePpiList (
  29   OUT UINTN                   *PpiListSize,
  30   OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
  31   )
  32 {
  33   EFI_PEI_PPI_DESCRIPTOR  *PlatformPpiList;
  34   UINTN                   PlatformPpiListSize;
  35   UINTN                   ListBase;
  36   EFI_PEI_PPI_DESCRIPTOR  *LastPpi;
  37
  38   // Get the Platform PPIs
  39   PlatformPpiListSize = 0;
  40   ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);
  41
  42   // Copy the Common and Platform PPis in Temporary Memory
  43   ListBase = PcdGet64 (PcdCPUCoresStackBase);
  44   CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));
  45   CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);
  46
  47   // Set the Terminate flag on the last PPI entry
  48   LastPpi         = (EFI_PEI_PPI_DESCRIPTOR *)ListBase + ((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;
  49   LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
  50
  51   *PpiList     = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;
  52   *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;
  53 }
  54
  55 VOID
  56 CEntryPoint (
  57   IN  UINTN                     MpId,
  58   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
  59   )
  60 {
  61   // Data Cache enabled on Primary core when MMU is enabled.
  62   ArmDisableDataCache ();
  63   // Invalidate instruction cache
  64   ArmInvalidateInstructionCache ();
  65   // Enable Instruction Caches on all cores.
  66   ArmEnableInstructionCache ();
  67
  68   InvalidateDataCacheRange (
  69     (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
  70     PcdGet32 (PcdCPUCorePrimaryStackSize)
  71     );
  72
  73   //
  74   // Note: Doesn't have to Enable CPU interface in non-secure world,
  75   // as Non-secure interface is already enabled in Secure world.
  76   //
  77
  78   // Write VBAR - The Exception Vector table must be aligned to its requirement
  79   // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
  80   // 'Align=4K' is defined into your FDF for this module.
  81   ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
  82   ArmWriteVBar ((UINTN)PeiVectorTable);
  83
  84   // Enable Floating Point
  85   if (FixedPcdGet32 (PcdVFPEnabled)) {
  86     ArmEnableVFP ();
  87   }
  88
  89   // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
  90
  91   // If not primary Jump to Secondary Main
  92   if (ArmPlatformIsPrimaryCore (MpId)) {
  93     // Invoke "ProcessLibraryConstructorList" to have all library constructors
  94     // called.
  95     ProcessLibraryConstructorList ();
  96
  97     // Initialize the Debug Agent for Source Level Debugging
  98     InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
  99     SaveAndSetDebugTimerInterrupt (TRUE);
 100
 101     // Initialize the platform specific controllers
 102     ArmPlatformInitialize (MpId);
 103
 104     // Goto primary Main.
 105     PrimaryMain (PeiCoreEntryPoint);
 106   } else {
 107     SecondaryMain (MpId);
 108   }
 109
 110   // PEI Core should always load and never return
 111   ASSERT (FALSE);
 112 }
 113
 114 EFI_STATUS
 115 EFIAPI
 116 PrePeiCoreTemporaryRamSupport (
 117   IN CONST EFI_PEI_SERVICES  **PeiServices,
 118   IN EFI_PHYSICAL_ADDRESS    TemporaryMemoryBase,
 119   IN EFI_PHYSICAL_ADDRESS    PermanentMemoryBase,
 120   IN UINTN                   CopySize
 121   )
 122 {
 123   VOID   *OldHeap;
 124   VOID   *NewHeap;
 125   VOID   *OldStack;
 126   VOID   *NewStack;
 127   UINTN  HeapSize;
 128
 129   HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);
 130
 131   OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;
 132   NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));
 133
 134   OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);
 135   NewStack = (VOID *)(UINTN)PermanentMemoryBase;
 136
 137   //
 138   // Migrate the temporary memory stack to permanent memory stack.
 139   //
 140   CopyMem (NewStack, OldStack, CopySize - HeapSize);
 141
 142   //
 143   // Migrate the temporary memory heap to permanent memory heap.
 144   //
 145   CopyMem (NewHeap, OldHeap, HeapSize);
 146
 147   SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);
 148
 149   return EFI_SUCCESS;
 150 }