3 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Library/ArmGicLib.h>
19 #include <Ppi/ArmMpCoreInfo.h>
23 IN UINTN UefiMemoryBase
,
25 IN UINTN GlobalVariableBase
,
26 IN UINT64 StartTimeStamp
29 // Enable the GIC Distributor
30 ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase
));
32 // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization
33 if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores
)) {
34 // Sending SGI to all the Secondary CPU interfaces
35 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase
), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE
, 0x0E, PcdGet32 (PcdGicSgiIntId
));
38 PrePiMain (UefiMemoryBase
, StacksBase
, GlobalVariableBase
, StartTimeStamp
);
40 // We must never return
50 ARM_MP_CORE_INFO_PPI
*ArmMpCoreInfoPpi
;
53 ARM_CORE_INFO
*ArmCoreInfoTable
;
56 VOID (*SecondaryStart
)(VOID
);
57 UINTN SecondaryEntryAddr
;
58 UINTN AcknowledgeInterrupt
;
61 ClusterId
= GET_CLUSTER_ID(MpId
);
62 CoreId
= GET_CORE_ID(MpId
);
64 // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
65 Status
= GetPlatformPpi (&gArmMpCoreInfoPpiGuid
, (VOID
**)&ArmMpCoreInfoPpi
);
66 ASSERT_EFI_ERROR (Status
);
69 Status
= ArmMpCoreInfoPpi
->GetMpCoreInfo (&ArmCoreCount
, &ArmCoreInfoTable
);
70 ASSERT_EFI_ERROR (Status
);
72 // Find the core in the ArmCoreTable
73 for (Index
= 0; Index
< ArmCoreCount
; Index
++) {
74 if ((ArmCoreInfoTable
[Index
].ClusterId
== ClusterId
) && (ArmCoreInfoTable
[Index
].CoreId
== CoreId
)) {
79 // The ARM Core Info Table must define every core
80 ASSERT (Index
!= ArmCoreCount
);
82 // Clear Secondary cores MailBox
83 MmioWrite32 (ArmCoreInfoTable
[Index
].MailboxClearAddress
, ArmCoreInfoTable
[Index
].MailboxClearValue
);
89 SecondaryEntryAddr
= MmioRead32 (ArmCoreInfoTable
[Index
].MailboxGetAddress
);
91 // Acknowledge the interrupt and send End of Interrupt signal.
92 AcknowledgeInterrupt
= ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase
), &InterruptId
);
93 // Check if it is a valid interrupt ID
94 if (InterruptId
< ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase
))) {
95 // Got a valid SGI number hence signal End of Interrupt
96 ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase
), AcknowledgeInterrupt
);
98 } while (SecondaryEntryAddr
== 0);
100 // Jump to secondary core entry point.
101 SecondaryStart
= (VOID (*)())SecondaryEntryAddr
;
104 // The secondaries shouldn't reach here