3 * Copyright (c) 2011-2017, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Library/DebugAgentLib.h>
18 #include <Library/PrePiLib.h>
19 #include <Library/PrintLib.h>
20 #include <Library/PrePiHobListPointerLib.h>
21 #include <Library/TimerLib.h>
22 #include <Library/PerformanceLib.h>
24 #include <Ppi/GuidedSectionExtraction.h>
25 #include <Ppi/ArmMpCoreInfo.h>
26 #include <Ppi/SecPerformance.h>
30 #define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \
31 ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet64 (PcdSystemMemoryBase)))
33 UINT64 mSystemMemoryEnd
= FixedPcdGet64(PcdSystemMemoryBase
) +
34 FixedPcdGet64(PcdSystemMemorySize
) - 1;
44 EFI_PEI_PPI_DESCRIPTOR
*PpiList
;
48 ArmPlatformGetPlatformPpiList (&PpiListSize
, &PpiList
);
49 PpiListCount
= PpiListSize
/ sizeof(EFI_PEI_PPI_DESCRIPTOR
);
50 for (Index
= 0; Index
< PpiListCount
; Index
++, PpiList
++) {
51 if (CompareGuid (PpiList
->Guid
, PpiGuid
) == TRUE
) {
62 IN UINTN UefiMemoryBase
,
64 IN UINT64 StartTimeStamp
67 EFI_HOB_HANDOFF_INFO_TABLE
* HobList
;
68 ARM_MP_CORE_INFO_PPI
* ArmMpCoreInfoPpi
;
70 ARM_CORE_INFO
* ArmCoreInfoTable
;
75 FIRMWARE_SEC_PERFORMANCE Performance
;
77 // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
79 ((FixedPcdGet64 (PcdFdBaseAddress
) >= FixedPcdGet64 (PcdSystemMemoryBase
)) &&
80 ((UINT64
)(FixedPcdGet64 (PcdFdBaseAddress
) + FixedPcdGet32 (PcdFdSize
)) <= (UINT64
)mSystemMemoryEnd
)));
82 // Initialize the architecture specific bits
85 // Initialize the Serial Port
86 SerialPortInitialize ();
87 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"UEFI firmware (version %s built at %a on %a)\n\r",
88 (CHAR16
*)PcdGetPtr(PcdFirmwareVersionString
), __TIME__
, __DATE__
);
89 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);
91 // Initialize the Debug Agent for Source Level Debugging
92 InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC
, NULL
, NULL
);
93 SaveAndSetDebugTimerInterrupt (TRUE
);
95 // Declare the PI/UEFI memory region
96 HobList
= HobConstructor (
97 (VOID
*)UefiMemoryBase
,
98 FixedPcdGet32 (PcdSystemMemoryUefiRegionSize
),
99 (VOID
*)UefiMemoryBase
,
100 (VOID
*)StacksBase
// The top of the UEFI Memory is reserved for the stacks
102 PrePeiSetHobList (HobList
);
104 // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
105 Status
= MemoryPeim (UefiMemoryBase
, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize
));
106 ASSERT_EFI_ERROR (Status
);
108 // Create the Stacks HOB (reserve the memory for all stacks)
109 if (ArmIsMpCore ()) {
110 StacksSize
= PcdGet32 (PcdCPUCorePrimaryStackSize
) +
111 ((FixedPcdGet32 (PcdCoreCount
) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize
));
113 StacksSize
= PcdGet32 (PcdCPUCorePrimaryStackSize
);
115 BuildStackHob (StacksBase
, StacksSize
);
117 //TODO: Call CpuPei as a library
118 BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize
), PcdGet8 (PcdPrePiCpuIoSize
));
120 if (ArmIsMpCore ()) {
121 // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
122 Status
= GetPlatformPpi (&gArmMpCoreInfoPpiGuid
, (VOID
**)&ArmMpCoreInfoPpi
);
124 // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
125 ASSERT_EFI_ERROR (Status
);
127 // Build the MP Core Info Table
129 Status
= ArmMpCoreInfoPpi
->GetMpCoreInfo (&ArmCoreCount
, &ArmCoreInfoTable
);
130 if (!EFI_ERROR(Status
) && (ArmCoreCount
> 0)) {
131 // Build MPCore Info HOB
132 BuildGuidDataHob (&gArmMpCoreInfoGuid
, ArmCoreInfoTable
, sizeof (ARM_CORE_INFO
) * ArmCoreCount
);
136 // Store timer value logged at the beginning of firmware image execution
137 Performance
.ResetEnd
= GetTimeInNanoSecond (StartTimeStamp
);
139 // Build SEC Performance Data Hob
140 BuildGuidDataHob (&gEfiFirmwarePerformanceGuid
, &Performance
, sizeof (Performance
));
143 SetBootMode (ArmPlatformGetBootMode ());
145 // Initialize Platform HOBs (CpuHob and FvHob)
146 Status
= PlatformPeim ();
147 ASSERT_EFI_ERROR (Status
);
149 // Now, the HOB List has been initialized, we can register performance information
150 PERF_START (NULL
, "PEI", NULL
, StartTimeStamp
);
152 // SEC phase needs to run library constructors by hand.
153 ProcessLibraryConstructorList ();
155 // Assume the FV that contains the SEC (our code) also contains a compressed FV.
156 Status
= DecompressFirstFv ();
157 ASSERT_EFI_ERROR (Status
);
159 // Load the DXE Core and transfer control to it
160 Status
= LoadDxeCoreFromFv (NULL
, 0);
161 ASSERT_EFI_ERROR (Status
);
167 IN UINTN UefiMemoryBase
,
171 UINT64 StartTimeStamp
;
173 // Initialize the platform specific controllers
174 ArmPlatformInitialize (MpId
);
176 if (ArmPlatformIsPrimaryCore (MpId
) && PerformanceMeasurementEnabled ()) {
177 // Initialize the Timer Library to setup the Timer HW controller
179 // We cannot call yet the PerformanceLib because the HOB List has not been initialized
180 StartTimeStamp
= GetPerformanceCounter ();
185 // Data Cache enabled on Primary core when MMU is enabled.
186 ArmDisableDataCache ();
187 // Invalidate Data cache
188 ArmInvalidateDataCache ();
189 // Invalidate instruction cache
190 ArmInvalidateInstructionCache ();
191 // Enable Instruction Caches on all cores.
192 ArmEnableInstructionCache ();
194 // Define the Global Variable region when we are not running in XIP
196 if (ArmPlatformIsPrimaryCore (MpId
)) {
198 // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
202 // Wait the Primay core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)
207 // If not primary Jump to Secondary Main
208 if (ArmPlatformIsPrimaryCore (MpId
)) {
209 // Goto primary Main.
210 PrimaryMain (UefiMemoryBase
, StacksBase
, StartTimeStamp
);
212 SecondaryMain (MpId
);
215 // DXE Core should always load and never return