2 * Main file supporting the SEC Phase on ARM Platforms
4 * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Library/ArmTrustedMonitorLib.h>
17 #include <Library/DebugAgentLib.h>
18 #include <Library/PrintLib.h>
19 #include <Library/BaseMemoryLib.h>
20 #include <Library/SerialPortLib.h>
21 #include <Library/ArmGicLib.h>
23 #include "SecInternal.h"
25 #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
37 // Invalidate the data cache. Doesn't have to do the Data cache clean.
38 ArmInvalidateDataCache ();
40 // Invalidate Instruction Cache
41 ArmInvalidateInstructionCache ();
43 // Invalidate I & D TLBs
44 ArmInvalidateInstructionAndDataTlb ();
46 // CPU specific settings
49 // Enable Floating Point Coprocessor if supported by the platform
50 if (FixedPcdGet32 (PcdVFPEnabled
)) {
54 // Initialize peripherals that must be done at the early stage
55 // Example: Some L2 controller, interconnect, clock, DMC, etc
56 ArmPlatformSecInitialize (MpId
);
58 // Primary CPU clears out the SCU tag RAMs, secondaries wait
59 if (ArmPlatformIsPrimaryCore (MpId
) && (SecBootMode
== ARM_SEC_COLD_BOOT
)) {
61 // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
65 // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
66 // In non SEC modules the init call is in autogenerated code.
67 SerialPortInitialize ();
70 if (FixedPcdGetBool (PcdTrustzoneSupport
)) {
71 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Secure firmware (version %s built at %a on %a)\n\r",
72 (CHAR16
*)PcdGetPtr(PcdFirmwareVersionString
), __TIME__
, __DATE__
);
74 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Boot firmware (version %s built at %a on %a)\n\r",
75 (CHAR16
*)PcdGetPtr(PcdFirmwareVersionString
), __TIME__
, __DATE__
);
77 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);
79 // Initialize the Debug Agent for Source Level Debugging
80 InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC
, NULL
, NULL
);
81 SaveAndSetDebugTimerInterrupt (TRUE
);
83 // Enable the GIC distributor and CPU Interface
84 // - no other Interrupts are enabled, doesn't have to worry about the priority.
85 // - all the cores are in secure state, use secure SGI's
86 ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase
));
87 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase
));
89 // Enable the GIC CPU Interface
90 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase
));
93 // Enable Full Access to CoProcessors
94 ArmWriteCpacr (CPACR_CP_FULL_ACCESS
);
96 // Test if Trustzone is supported on this platform
97 if (FixedPcdGetBool (PcdTrustzoneSupport
)) {
99 // Setup SMP in Non Secure world
100 ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId
));
103 // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
104 // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
105 ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase
) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize
) == 0)) ||
106 ((PcdGet32(PcdCPUCoresSecMonStackBase
) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize
) != 0)));
108 // Enter Monitor Mode
109 enter_monitor_mode ((UINTN
)TrustedWorldInitialization
, MpId
, SecBootMode
, (VOID
*)(PcdGet32(PcdCPUCoresSecMonStackBase
) + (PcdGet32(PcdCPUCoreSecMonStackSize
) * (GET_CORE_POS(MpId
) + 1))));
111 if (ArmPlatformIsPrimaryCore (MpId
)) {
112 SerialPrint ("Trust Zone Configuration is disabled\n\r");
115 // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
116 // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
117 // Status Register as the the current one (CPSR).
118 copy_cpsr_into_spsr ();
120 // Call the Platform specific function to execute additional actions if required
121 JumpAddress
= PcdGet32 (PcdFvBaseAddress
);
122 ArmPlatformSecExtraAction (MpId
, &JumpAddress
);
124 NonTrustedWorldTransition (MpId
, JumpAddress
);
126 ASSERT (0); // We must never return from the above function
130 TrustedWorldInitialization (
137 //-------------------- Monitor Mode ---------------------
139 // Set up Monitor World (Vector Table, etc)
140 ArmSecureMonitorWorldInitialize ();
142 // Transfer the interrupt to Non-secure World
143 ArmGicSetupNonSecure (MpId
, PcdGet32(PcdGicDistributorBase
), PcdGet32(PcdGicInterruptInterfaceBase
));
145 // Initialize platform specific security policy
146 ArmPlatformSecTrustzoneInit (MpId
);
148 // Setup the Trustzone Chipsets
149 if (SecBootMode
== ARM_SEC_COLD_BOOT
) {
150 if (ArmPlatformIsPrimaryCore (MpId
)) {
152 // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
156 // The secondary cores need to wait until the Trustzone chipsets configuration is done
157 // before switching to Non Secure World
159 // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
164 // Call the Platform specific function to execute additional actions if required
165 JumpAddress
= PcdGet32 (PcdFvBaseAddress
);
166 ArmPlatformSecExtraAction (MpId
, &JumpAddress
);
168 // Initialize architecture specific security policy
169 ArmSecArchTrustzoneInit ();
171 // CP15 Secure Configuration Register
172 ArmWriteScr (PcdGet32 (PcdArmScr
));
174 NonTrustedWorldTransition (MpId
, JumpAddress
);
178 NonTrustedWorldTransition (
183 // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
184 // By not set, the mode for Non Secure World is SVC
185 if (PcdGet32 (PcdArmNonSecModeTransition
) != 0) {
186 set_non_secure_mode ((ARM_PROCESSOR_MODE
)PcdGet32 (PcdArmNonSecModeTransition
));
189 return_from_exception (JumpAddress
);
190 //-------------------- Non Secure Mode ---------------------
192 // PEI Core should always load and never return