2 * Main file supporting the SEC Phase on ARM Platforms
4 * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Library/ArmTrustedMonitorLib.h>
17 #include <Library/DebugAgentLib.h>
18 #include <Library/PrintLib.h>
19 #include <Library/BaseMemoryLib.h>
20 #include <Library/SerialPortLib.h>
21 #include <Library/ArmGicLib.h>
22 #include <Library/ArmCpuLib.h>
24 #include "SecInternal.h"
26 #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
37 // Invalidate the data cache. Doesn't have to do the Data cache clean.
38 ArmInvalidateDataCache();
40 // Invalidate Instruction Cache
41 ArmInvalidateInstructionCache();
43 // Invalidate I & D TLBs
44 ArmInvalidateInstructionAndDataTlb();
46 // CPU specific settings
49 // Enable Floating Point Coprocessor if supported by the platform
50 if (FixedPcdGet32 (PcdVFPEnabled
)) {
54 // Primary CPU clears out the SCU tag RAMs, secondaries wait
55 if (IS_PRIMARY_CORE(MpId
)) {
57 ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT
);
60 // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
61 // In non SEC modules the init call is in autogenerated code.
62 SerialPortInitialize ();
65 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"UEFI firmware built at %a on %a\n\r",__TIME__
, __DATE__
);
66 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);
68 // Initialize the Debug Agent for Source Level Debugging
69 InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC
, NULL
, NULL
);
70 SaveAndSetDebugTimerInterrupt (TRUE
);
72 // Now we've got UART, make the check:
73 // - The Vector table must be 32-byte aligned
74 ASSERT(((UINT32
)SecVectorTable
& ((1 << 5)-1)) == 0);
76 // Enable the GIC distributor and CPU Interface
77 // - no other Interrupts are enabled, doesn't have to worry about the priority.
78 // - all the cores are in secure state, use secure SGI's
79 ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase
));
80 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase
));
82 // Enable the GIC CPU Interface
83 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase
));
86 // Enable Full Access to CoProcessors
87 ArmWriteCPACR (CPACR_CP_FULL_ACCESS
);
89 if (IS_PRIMARY_CORE(MpId
)) {
90 // Initialize peripherals that must be done at the early stage
91 // Example: Some L2x0 controllers must be initialized in Secure World
92 ArmPlatformSecInitialize ();
94 // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
95 // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
96 if (FeaturePcdGet (PcdSystemMemoryInitializeInSec
)) {
97 // Initialize system memory (DRAM)
98 ArmPlatformInitializeSystemMemory ();
102 // Test if Trustzone is supported on this platform
103 if (FixedPcdGetBool (PcdTrustzoneSupport
)) {
105 // Setup SMP in Non Secure world
106 ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId
));
109 // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
110 // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
111 ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase
) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize
) == 0)) ||
112 ((PcdGet32(PcdCPUCoresSecMonStackBase
) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize
) != 0)));
114 // Enter Monitor Mode
115 enter_monitor_mode ((UINTN
)TrustedWorldInitialization
, MpId
, (VOID
*)(PcdGet32(PcdCPUCoresSecMonStackBase
) + (PcdGet32(PcdCPUCoreSecMonStackSize
) * (GET_CORE_POS(MpId
) + 1))));
117 if (IS_PRIMARY_CORE(MpId
)) {
118 SerialPrint ("Trust Zone Configuration is disabled\n\r");
121 // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
122 // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
123 // Status Register as the the current one (CPSR).
124 copy_cpsr_into_spsr ();
126 // Call the Platform specific function to execute additional actions if required
127 JumpAddress
= PcdGet32 (PcdFvBaseAddress
);
128 ArmPlatformSecExtraAction (MpId
, &JumpAddress
);
130 NonTrustedWorldTransition (MpId
, JumpAddress
);
132 ASSERT (0); // We must never return from the above function
136 TrustedWorldInitialization (
142 //-------------------- Monitor Mode ---------------------
144 // Set up Monitor World (Vector Table, etc)
145 ArmSecureMonitorWorldInitialize ();
147 // Transfer the interrupt to Non-secure World
148 ArmGicSetupNonSecure (MpId
, PcdGet32(PcdGicDistributorBase
), PcdGet32(PcdGicInterruptInterfaceBase
));
150 // Initialize platform specific security policy
151 ArmPlatformTrustzoneInit (MpId
);
153 // Setup the Trustzone Chipsets
154 if (IS_PRIMARY_CORE(MpId
)) {
156 // Waiting for the Primary Core to have finished to initialize the Secure World
157 ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT
);
160 // The secondary cores need to wait until the Trustzone chipsets configuration is done
161 // before switching to Non Secure World
163 // Waiting for the Primary Core to have finished to initialize the Secure World
164 ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT
);
167 // Call the Platform specific fucntion to execute additional actions if required
168 JumpAddress
= PcdGet32 (PcdFvBaseAddress
);
169 ArmPlatformSecExtraAction (MpId
, &JumpAddress
);
171 // Write to CP15 Non-secure Access Control Register
172 ArmWriteNsacr (PcdGet32 (PcdArmNsacr
));
174 // CP15 Secure Configuration Register
175 ArmWriteScr (PcdGet32 (PcdArmScr
));
177 NonTrustedWorldTransition (MpId
, JumpAddress
);
181 NonTrustedWorldTransition (
186 // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
187 // By not set, the mode for Non Secure World is SVC
188 if (PcdGet32 (PcdArmNonSecModeTransition
) != 0) {
189 set_non_secure_mode ((ARM_PROCESSOR_MODE
)PcdGet32 (PcdArmNonSecModeTransition
));
192 return_from_exception (JumpAddress
);
193 //-------------------- Non Secure Mode ---------------------
195 // PEI Core should always load and never return
200 SecCommonExceptionEntry (
210 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Reset Exception at 0x%X\n\r",LR
);
213 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Undefined Exception at 0x%X\n\r",LR
);
216 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"SWI Exception at 0x%X\n\r",LR
);
219 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"PrefetchAbort Exception at 0x%X\n\r",LR
);
222 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"DataAbort Exception at 0x%X\n\r",LR
);
225 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Reserved Exception at 0x%X\n\r",LR
);
228 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"IRQ Exception at 0x%X\n\r",LR
);
231 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"FIQ Exception at 0x%X\n\r",LR
);
234 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"Unknown Exception at 0x%X\n\r",LR
);
237 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);