2 // Copyright (c) 2011-2012, ARM Limited. All rights reserved.
4 // This program and the accompanying materials
5 // are licensed and made available under the terms and conditions of the BSD License
6 // which accompanies this distribution. The full text of the license may be found at
7 // http://opensource.org/licenses/bsd-license.php
9 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <AsmMacroIoLib.h>
16 #include "SecInternal.h"
21 GCC_ASM_IMPORT(CEntryPoint)
22 GCC_ASM_IMPORT(ArmPlatformSecBootAction)
23 GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)
24 GCC_ASM_IMPORT(ArmDisableInterrupts)
25 GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
26 GCC_ASM_IMPORT(ArmReadMpidr)
27 GCC_ASM_IMPORT(ArmCallWFE)
28 GCC_ASM_EXPORT(_ModuleEntryPoint)
30 StartupAddr: .word ASM_PFX(CEntryPoint)
32 ASM_PFX(_ModuleEntryPoint):
33 // First ensure all interrupts are disabled
34 bl ASM_PFX(ArmDisableInterrupts)
36 // Ensure that the MMU and caches are off
37 bl ASM_PFX(ArmDisableCachesAndMmu)
39 // By default, we are doing a cold boot
40 mov r10, #ARM_SEC_COLD_BOOT
42 // Jump to Platform Specific Boot Action function
43 blx ASM_PFX(ArmPlatformSecBootAction)
47 bl ASM_PFX(ArmReadMpidr)
48 // Get ID of this CPU in Multicore system
49 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
52 // Is it the Primary Core ?
53 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)
55 // Only the primary core initialize the memory (SMC)
59 // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
60 // Otherwise we have to wait the Primary Core to finish the initialization
61 cmp r10, #ARM_SEC_COLD_BOOT
62 bne _SetupSecondaryCoreStack
64 // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
65 bl ASM_PFX(ArmCallWFE)
66 // Now the Init Mem is initialized, we setup the secondary core stacks
67 b _SetupSecondaryCoreStack
70 // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
71 cmp r10, #ARM_SEC_COLD_BOOT
72 bne _SetupPrimaryCoreStack
74 // Initialize Init Boot Memory
75 bl ASM_PFX(ArmPlatformSecBootMemoryInit)
77 // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
78 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
80 _SetupPrimaryCoreStack:
81 // Get the top of the primary stacks (and the base of the secondary stacks)
82 LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
83 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
86 LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)
88 // The reserved space for global variable must be 8-bytes aligned for pushing
89 // 64-bit variable on the stack
90 SetPrimaryStack (r1, r2, r3)
93 _SetupSecondaryCoreStack:
94 // Get the top of the primary stacks (and the base of the secondary stacks)
95 LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
96 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
99 // Get the Core Position (ClusterId * 4) + CoreId
100 GetCorePositionFromMpId(r0, r5, r2)
101 // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
104 // StackOffset = CorePos * StackSize
105 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
107 // SP = StackBase + StackOffset
111 // Move sec startup address into a data register
112 // Ensure we're jumping to FV version of the code (not boot remapped alias)
115 // Jump to SEC C code