ArmPlatformPkg/Sec/SecEntryPoint.asm

   1 //
   2 //  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AutoGen.h>
  15 #include <AsmMacroIoLib.h>
  16 #include "SecInternal.h"
  17
  18   INCLUDE AsmMacroIoLib.inc
  19
  20   IMPORT  CEntryPoint
  21   IMPORT  ArmPlatformSecBootAction
  22   IMPORT  ArmPlatformInitializeBootMemory
  23   IMPORT  ArmDisableInterrupts
  24   IMPORT  ArmDisableCachesAndMmu
  25   IMPORT  ArmWriteVBar
  26   IMPORT  ArmReadMpidr
  27   IMPORT  SecVectorTable
  28   IMPORT  ArmCpuSynchronizeWait
  29   EXPORT  _ModuleEntryPoint
  30
  31   PRESERVE8
  32   AREA    SecEntryPoint, CODE, READONLY
  33
  34 StartupAddr        DCD      CEntryPoint
  35
  36 _ModuleEntryPoint
  37   // First ensure all interrupts are disabled
  38   blx   ArmDisableInterrupts
  39
  40   // Ensure that the MMU and caches are off
  41   blx   ArmDisableCachesAndMmu
  42
  43   // Jump to Platform Specific Boot Action function
  44   blx   ArmPlatformSecBootAction
  45
  46   // Set VBAR to the start of the exception vectors in Secure Mode
  47   ldr   r0, =SecVectorTable
  48   blx   ArmWriteVBar
  49
  50 _IdentifyCpu
  51   // Identify CPU ID
  52   bl    ArmReadMpidr
  53   // Get ID of this CPU in Multicore system
  54   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
  55   and   r5, r0, r1
  56
  57   // Is it the Primary Core ?
  58   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
  59   cmp   r5, r1
  60   // Only the primary core initialize the memory (SMC)
  61   beq   _InitMem
  62
  63 _WaitInitMem
  64   mov   r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
  65   bl    ArmCpuSynchronizeWait
  66   // Now the Init Mem is initialized, we setup the secondary core stacks
  67   b     _SetupSecondaryCoreStack
  68
  69 _InitMem
  70   // Initialize Init Boot Memory
  71   bl    ArmPlatformInitializeBootMemory
  72
  73   // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
  74   LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
  75
  76 _SetupPrimaryCoreStack
  77   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)
  78   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)
  79   // Calculate the Top of the Stack
  80   add   r2, r2, r3
  81   LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)
  82
  83   // The reserved space for global variable must be 8-bytes aligned for pushing
  84   // 64-bit variable on the stack
  85   SetPrimaryStack (r2, r3, r1)
  86
  87   // Set all the SEC global variables to 0
  88   mov     r3, sp
  89   mov     r1, #0x0
  90 _InitGlobals
  91   str     r1, [r3], #4
  92   cmp     r3, r2
  93   bne     _InitGlobals
  94
  95   b     _PrepareArguments
  96
  97 _SetupSecondaryCoreStack
  98   // Get the Core Position (ClusterId * 4) + CoreId
  99   GetCorePositionInStack(r0, r5, r1)
 100   // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
 101   add   r0, r0, #1
 102
 103   // Get the base of the stack for the secondary cores
 104   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
 105   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
 106   add   r1, r1, r2
 107
 108   // StackOffset = CorePos * StackSize
 109   mul   r0, r0, r2
 110   // SP = StackBase + StackOffset
 111   add   sp, r1, r0
 112
 113
 114 _PrepareArguments
 115   // Move sec startup address into a data register
 116   // Ensure we're jumping to FV version of the code (not boot remapped alias)
 117   ldr   r3, StartupAddr
 118
 119   // Jump to SEC C code
 120   //    r0 = mp_id
 121   mov   r0, r5
 122   blx   r3
 123
 124 _NeverReturn
 125   b _NeverReturn
 126   END