2 // Copyright (c) 2011-2012, ARM Limited. All rights reserved.
4 // This program and the accompanying materials
5 // are licensed and made available under the terms and conditions of the BSD License
6 // which accompanies this distribution. The full text of the license may be found at
7 // http://opensource.org/licenses/bsd-license.php
9 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <AsmMacroIoLib.h>
16 #include "SecInternal.h"
18 INCLUDE AsmMacroIoLib.inc
21 IMPORT ArmPlatformSecBootAction
22 IMPORT ArmPlatformSecBootMemoryInit
23 IMPORT ArmDisableInterrupts
24 IMPORT ArmDisableCachesAndMmu
29 EXPORT _ModuleEntryPoint
32 AREA SecEntryPoint, CODE, READONLY
34 StartupAddr DCD CEntryPoint
36 _ModuleEntryPoint FUNCTION
37 // First ensure all interrupts are disabled
38 blx ArmDisableInterrupts
40 // Ensure that the MMU and caches are off
41 blx ArmDisableCachesAndMmu
43 // By default, we are doing a cold boot
44 mov r10, #ARM_SEC_COLD_BOOT
46 // Jump to Platform Specific Boot Action function
47 blx ArmPlatformSecBootAction
49 // Set VBAR to the start of the exception vectors in Secure Mode
50 ldr r0, =SecVectorTable
56 // Get ID of this CPU in Multicore system
57 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
60 // Is it the Primary Core ?
61 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)
63 // Only the primary core initialize the memory (SMC)
67 // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
68 // Otherwise we have to wait the Primary Core to finish the initialization
69 cmp r10, #ARM_SEC_COLD_BOOT
70 bne _SetupSecondaryCoreStack
72 // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
74 // Now the Init Mem is initialized, we setup the secondary core stacks
75 b _SetupSecondaryCoreStack
78 // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
79 cmp r10, #ARM_SEC_COLD_BOOT
80 bne _SetupPrimaryCoreStack
82 // Initialize Init Boot Memory
83 bl ArmPlatformSecBootMemoryInit
85 // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
86 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
88 _SetupPrimaryCoreStack
89 // Get the top of the primary stacks (and the base of the secondary stacks)
90 LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
91 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
94 LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)
96 // The reserved space for global variable must be 8-bytes aligned for pushing
97 // 64-bit variable on the stack
98 SetPrimaryStack (r1, r2, r3)
101 _SetupSecondaryCoreStack
102 // Get the top of the primary stacks (and the base of the secondary stacks)
103 LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
104 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
107 // Get the Core Position (ClusterId * 4) + CoreId
108 GetCorePositionFromMpId(r0, r5, r2)
109 // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
112 // StackOffset = CorePos * StackSize
113 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
115 // SP = StackBase + StackOffset
119 // Move sec startup address into a data register
120 // Ensure we're jumping to FV version of the code (not boot remapped alias)
123 // Jump to SEC C code