3 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Pi/PiBootMode.h>
18 #include <Library/PrePiLib.h>
19 #include <Library/PrintLib.h>
20 #include <Library/PrePiHobListPointerLib.h>
21 #include <Library/TimerLib.h>
22 #include <Library/PerformanceLib.h>
23 #include <Library/CacheMaintenanceLib.h>
25 #include <Ppi/GuidedSectionExtraction.h>
26 #include <Ppi/ArmMpCoreInfo.h>
32 ProcessLibraryConstructorList (
38 IN UINTN UefiMemoryBase
,
40 IN UINT64 StartTimeStamp
43 EFI_HOB_HANDOFF_INFO_TABLE
* HobList
;
49 // Initialize the architecture specific bits
52 // Declare the PI/UEFI memory region
53 HobList
= HobConstructor (
54 (VOID
*)UefiMemoryBase
,
55 FixedPcdGet32 (PcdSystemMemoryUefiRegionSize
),
56 (VOID
*)UefiMemoryBase
,
57 (VOID
*)StacksBase
// The top of the UEFI Memory is reserved for the stacks
59 PrePeiSetHobList (HobList
);
62 // Ensure that the loaded image is invalidated in the caches, so that any
63 // modifications we made with the caches and MMU off (such as the applied
64 // relocations) don't become invisible once we turn them on.
66 InvalidateDataCacheRange((VOID
*)(UINTN
)PcdGet64 (PcdFdBaseAddress
), PcdGet32 (PcdFdSize
));
68 // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
69 Status
= MemoryPeim (UefiMemoryBase
, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize
));
70 ASSERT_EFI_ERROR (Status
);
72 // Initialize the Serial Port
73 SerialPortInitialize ();
74 CharCount
= AsciiSPrint (Buffer
,sizeof (Buffer
),"UEFI firmware (version %s built at %a on %a)\n\r",
75 (CHAR16
*)PcdGetPtr(PcdFirmwareVersionString
), __TIME__
, __DATE__
);
76 SerialPortWrite ((UINT8
*) Buffer
, CharCount
);
78 // Create the Stacks HOB (reserve the memory for all stacks)
79 StacksSize
= PcdGet32 (PcdCPUCorePrimaryStackSize
);
80 BuildStackHob (StacksBase
, StacksSize
);
82 //TODO: Call CpuPei as a library
83 BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize
), PcdGet8 (PcdPrePiCpuIoSize
));
86 SetBootMode (BOOT_WITH_FULL_CONFIGURATION
);
88 // Initialize Platform HOBs (CpuHob and FvHob)
89 Status
= PlatformPeim ();
90 ASSERT_EFI_ERROR (Status
);
92 // Now, the HOB List has been initialized, we can register performance information
93 PERF_START (NULL
, "PEI", NULL
, StartTimeStamp
);
95 // SEC phase needs to run library constructors by hand.
96 ProcessLibraryConstructorList ();
98 // Assume the FV that contains the SEC (our code) also contains a compressed FV.
99 Status
= DecompressFirstFv ();
100 ASSERT_EFI_ERROR (Status
);
102 // Load the DXE Core and transfer control to it
103 Status
= LoadDxeCoreFromFv (NULL
, 0);
104 ASSERT_EFI_ERROR (Status
);
110 IN UINTN UefiMemoryBase
,
114 UINT64 StartTimeStamp
;
116 if (PerformanceMeasurementEnabled ()) {
117 // Initialize the Timer Library to setup the Timer HW controller
119 // We cannot call yet the PerformanceLib because the HOB List has not been initialized
120 StartTimeStamp
= GetPerformanceCounter ();
125 // Data Cache enabled on Primary core when MMU is enabled.
126 ArmDisableDataCache ();
127 // Invalidate instruction cache
128 ArmInvalidateInstructionCache ();
129 // Enable Instruction Caches on all cores.
130 ArmEnableInstructionCache ();
132 PrePiMain (UefiMemoryBase
, StacksBase
, StartTimeStamp
);
134 // DXE Core should always load and never return