BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  SPDX-License-Identifier: BSD-2-Clause-Patent
   6 *
   7 **/
   8
   9 #include <Library/ArmPlatformLib.h>
  10 #include <Library/DebugLib.h>
  11 #include <Library/PcdLib.h>
  12 #include <Library/MemoryAllocationLib.h>
  13 #include <Library/IoLib.h>
  14
  15 #include <BeagleBoard.h>
  16
  17 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          4
  18
  19 /**
  20   Return the Virtual Memory Map of your platform
  21
  22   This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
  23
  24   @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
  25                                     Virtual Memory mapping. This array must be ended by a zero-filled
  26                                     entry
  27
  28 **/
  29 VOID
  30 ArmPlatformGetVirtualMemoryMap (
  31   IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
  32   )
  33 {
  34   ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
  35   UINTN                         Index = 0;
  36   ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
  37
  38   ASSERT(VirtualMemoryMap != NULL);
  39
  40   VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
  41   if (VirtualMemoryTable == NULL) {
  42     return;
  43   }
  44
  45   CacheAttributes = DDR_ATTRIBUTES_CACHED;
  46
  47   // ReMap (Either NOR Flash or DRAM)
  48   VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
  49   VirtualMemoryTable[Index].VirtualBase  = PcdGet64 (PcdSystemMemoryBase);
  50   VirtualMemoryTable[Index].Length       = PcdGet64 (PcdSystemMemorySize);
  51   VirtualMemoryTable[Index].Attributes   = CacheAttributes;
  52
  53   // SOC Registers. L3 interconnects
  54   VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
  55   VirtualMemoryTable[Index].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;
  56   VirtualMemoryTable[Index].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
  57   VirtualMemoryTable[Index].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;
  58
  59   // SOC Registers. L4 interconnects
  60   VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
  61   VirtualMemoryTable[Index].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;
  62   VirtualMemoryTable[Index].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
  63   VirtualMemoryTable[Index].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;
  64
  65   // End of Table
  66   VirtualMemoryTable[++Index].PhysicalBase = 0;
  67   VirtualMemoryTable[Index].VirtualBase  = 0;
  68   VirtualMemoryTable[Index].Length       = 0;
  69   VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
  70
  71   ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
  72
  73   *VirtualMemoryMap = VirtualMemoryTable;
  74 }