2 C Entry point for the SEC. First C code after the reset vector.
4 Copyright (c) 2008-2009, Apple Inc. All rights reserved.
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Library/DebugLib.h>
19 #include <Library/PrePiLib.h>
20 #include <Library/PcdLib.h>
21 #include <Library/IoLib.h>
22 #include <Library/OmapLib.h>
23 #include <Library/ArmLib.h>
25 #include <Ppi/GuidedSectionExtraction.h>
27 #include <Omap3530/Omap3530.h>
44 UINTN Timer
= FixedPcdGet32(PcdBeagleFreeTimer
);
45 UINT32 TimerBaseAddress
= TimerBase(Timer
);
47 // Set source clock for GPT3 & GPT4 to SYS_CLK
48 MmioOr32(CM_CLKSEL_PER
, CM_CLKSEL_PER_CLKSEL_GPT3_SYS
49 | CM_CLKSEL_PER_CLKSEL_GPT4_SYS
);
51 // Set count & reload registers
52 MmioWrite32(TimerBaseAddress
+ GPTIMER_TCRR
, 0x00000000);
53 MmioWrite32(TimerBaseAddress
+ GPTIMER_TLDR
, 0x00000000);
56 MmioWrite32(TimerBaseAddress
+ GPTIMER_TIER
, TIER_TCAR_IT_DISABLE
| TIER_OVF_IT_DISABLE
| TIER_MAT_IT_DISABLE
);
59 MmioWrite32(TimerBaseAddress
+ GPTIMER_TCLR
, TCLR_AR_AUTORELOAD
| TCLR_ST_ON
);
61 //Disable OMAP Watchdog timer (WDT2)
62 MmioWrite32(WDTIMER2_BASE
+ WSPR
, 0xAAAA);
63 DEBUG ((EFI_D_ERROR
, "Magic delay to disable watchdog timers properly.\n"));
64 MmioWrite32(WDTIMER2_BASE
+ WSPR
, 0x5555);
72 UINTN Uart
= FixedPcdGet32(PcdBeagleConsoleUart
);
73 UINT32 UartBaseAddress
= UartBase(Uart
);
75 // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.
76 MmioWrite32(UartBaseAddress
+ UART_MDR1_REG
, UART_MDR1_MODE_SELECT_DISABLE
);
78 // Put device in configuration mode.
79 MmioWrite32(UartBaseAddress
+ UART_LCR_REG
, UART_LCR_DIV_EN_ENABLE
);
81 // Programmable divisor N = 48Mhz/16/115200 = 26
82 MmioWrite32(UartBaseAddress
+ UART_DLL_REG
, 26); // low divisor
83 MmioWrite32(UartBaseAddress
+ UART_DLH_REG
, 0); // high divisor
85 // Enter into UART operational mode.
86 MmioWrite32(UartBaseAddress
+ UART_LCR_REG
, UART_LCR_DIV_EN_DISABLE
| UART_LCR_CHAR_LENGTH_8
);
88 // Force DTR and RTS output to active
89 MmioWrite32(UartBaseAddress
+ UART_MCR_REG
, UART_MCR_RTS_FORCE_ACTIVE
| UART_MCR_DTR_FORCE_ACTIVE
);
91 // Clear & enable fifos
92 MmioWrite32(UartBaseAddress
+ UART_FCR_REG
, UART_FCR_TX_FIFO_CLEAR
| UART_FCR_RX_FIFO_CLEAR
| UART_FCR_FIFO_ENABLE
);
94 // Restore MODE_SELECT
95 MmioWrite32(UartBaseAddress
+ UART_MDR1_REG
, UART_MDR1_MODE_SELECT_UART_16X
);
100 IN UINT32 MemoryBase
,
101 IN UINT32 MemoryLength
106 ExtractGuidedSectionLibConstructor (
112 LzmaDecompressLibConstructor (
129 // Set up system clocking
132 // Build a basic HOB list
133 HobBase
= (VOID
*)(UINTN
)(FixedPcdGet32(PcdEmbeddedFdBaseAddress
) + FixedPcdGet32(PcdEmbeddedFdSize
));
134 CreateHobList(MemoryBase
, MemorySize
, HobBase
, StackBase
);
136 // Enable program flow prediction, if supported.
137 ArmEnableBranchPrediction();
139 // Initialize CPU cache
140 InitCache((UINT32
)MemoryBase
, (UINT32
)MemorySize
);
142 // Add memory allocation hob for relocated FD
143 BuildMemoryAllocationHob(FixedPcdGet32(PcdEmbeddedFdBaseAddress
), FixedPcdGet32(PcdEmbeddedFdSize
), EfiBootServicesData
);
145 // Add the FVs to the hob list
146 BuildFvHob(PcdGet32(PcdFlashFvMainBase
), PcdGet32(PcdFlashFvMainSize
));
150 DEBUG((EFI_D_ERROR
, "UART Test Line\n"));
152 // Start up a free running time so that the timer lib will work
155 // SEC phase needs to run library constructors by hand.
156 ExtractGuidedSectionLibConstructor();
157 LzmaDecompressLibConstructor();
159 // Load the DXE Core and transfer control to it
160 LoadDxeCoreFromFv(NULL
, 0);
162 // DXE Core should always load and never return