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1 MediaTek Frame Engine Ethernet controller
2 =========================================
3
4 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
5 have dual GMAC each represented by a child node..
6
7 * Ethernet controller node
8
9 Required properties:
10 - compatible: Should be
11 "mediatek,mt2701-eth": for MT2701 SoC
12 "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
13 "mediatek,mt7622-eth": for MT7622 SoC
14 - reg: Address and length of the register set for the device
15 - interrupts: Should contain the three frame engines interrupts in numeric
16 order. These are fe_int0, fe_int1 and fe_int2.
17 - clocks: the clock used by the core
18 - clock-names: the names of the clock listed in the clocks property. These are
19 "ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC
20 "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
21 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
22 - power-domains: phandle to the power domain that the ethernet is part of
23 - resets: Should contain phandles to the ethsys reset signals
24 - reset-names: Should contain the names of reset signal listed in the resets
25 property
26 These are "fe", "gmac" and "ppe"
27 - mediatek,ethsys: phandle to the syscon node that handles the port setup
28 - mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
29 which is required for those SoCs equipped with SGMII such as MT7622 SoC.
30 - mediatek,pctl: phandle to the syscon node that handles the ports slew rate
31 and driver current
32
33 Optional properties:
34 - interrupt-parent: Should be the phandle for the interrupt controller
35 that services interrupts for this device
36 * Ethernet MAC node
37
38 Required properties:
39 - compatible: Should be "mediatek,eth-mac"
40 - reg: The number of the MAC
41 - phy-handle: see ethernet.txt file in the same directory and
42 the phy-mode "trgmii" required being provided when reg
43 is equal to 0 and the MAC uses fixed-link to connect
44 with internal switch such as MT7530.
45
46 Example:
47
48 eth: ethernet@1b100000 {
49 compatible = "mediatek,mt7623-eth";
50 reg = <0 0x1b100000 0 0x20000>;
51 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
52 <&ethsys CLK_ETHSYS_ESW>,
53 <&ethsys CLK_ETHSYS_GP2>,
54 <&ethsys CLK_ETHSYS_GP1>;
55 clock-names = "ethif", "esw", "gp2", "gp1";
56 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
57 GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
58 GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
59 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
60 resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
61 reset-names = "eth";
62 mediatek,ethsys = <&ethsys>;
63 mediatek,pctl = <&syscfg_pctl_a>;
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 gmac1: mac@0 {
68 compatible = "mediatek,eth-mac";
69 reg = <0>;
70 phy-handle = <&phy0>;
71 };
72
73 gmac2: mac@1 {
74 compatible = "mediatek,eth-mac";
75 reg = <1>;
76 phy-handle = <&phy1>;
77 };
78
79 mdio-bus {
80 phy0: ethernet-phy@0 {
81 reg = <0>;
82 phy-mode = "rgmii";
83 };
84
85 phy1: ethernet-phy@1 {
86 reg = <1>;
87 phy-mode = "rgmii";
88 };
89 };
90 };